AD5522

Preliminary Technical Data

Rev. PrL | Page 30 of 45

WRITE PMU REGISTER

To address PMU functions, set Mode bits MODE1, MODE0 low, this selects the PMU register as outlined in Table 13 and Table 14. The

AD5522 has very flexible addressing, in that it allows writing of data to a single PMU channel, any combination of them or all PMU

channels. This enables multi pin broadcasting to similar pins on a DUT. Bits 27 to 24 select which PMU or group of PMUs is addressed.

Table 17. PMU Register Bits

B28

B27

B26

B25

B24

B23

B22

B21

B20

B19

B18

B17

B16

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5 to B0

RD/WR

PMU3

PMU2

PMU1

PMU0

MODE1

MODE0

CH

EN

FORCE1

FORCE0

X

C2

C1

C0

MEAS1

MEAS0

FIN

SF0

SF0

CL

CPOLH

COMPARE

V/I

CLEAR

UNUSED

DATA

BITS

Table 18. PMU Register Functions

Bit

Bit name

Description

28

(MSB)

RD/WR

When low, a write function takes place to the selected register, while if the RD/WR bit is set high, this initiates a readback

sequence of PMU, Alarm, Comparator, System Control or DAC register as determined by address bits.

27

PMU3

26

PMU2

25

PMU1

24

PMU0

Bits PMU3 through PMU0 address each of the PMU channels in the device. This allows individual control of each PMU channel

or any manner of combined addressing in addition to multi-channel programming.

B27

B26

B25

B24

B23

B22

SELECTED REGISTER

PMU3

PMU2

PMU1

PMU0

MODE1

MODE0

CH3

CH2

CH1

CH0

0

0

0

0

0

0

Write to System Control Register

0

0

0

1

×

×

×

CHO

0

0

1

0

×

×

CH1

×

0

0

1

1

×

×

CH1

CH0

0

1

0

0

×

CH2

×

×

-

-

-

-

-

-

-

-

1

0

0

0

CH3

×

×

×

-

-

-

-

-

-

-

-

1

1

1

0

CH3

CH2

CH1

×

1

1

1

1

Select DAC or PMU Registers.

See below

CH3

CH2

CH1

CH0

23

MODE1

22

MODE0

Mode Bits, MODE0 and MODE1 allow addressing of the PMU register or the DAC gain (m), offset (c ) or input register (x1). Set

to zero to access the PMU Register.

MODE1

MODE0

Action

0

0

System Control Register or PMU Register

0

1

DAC Gain (m) Register

1

0

DAC Offset (c) Register

1

1

DAC Input Data Register, (x1)

PMU REGISTER SPECIFIC BITS

21

CH EN

Channel Enable, Set high to enable the selected channel, similarly, set low to disable a selected channel or group of channels.

When disabled, SW 2 is closed, SW 5 open.

20

FORCE1

19

FORCE0

Bits FORCE1 and FORCE0 address the force function for each of the PMU channels (in association with P3-P0). All

combinations of forcing and measuring (using MEAS0 and MEAS1) are available. The Hi-Z (voltage and current) modes allows

user to optimize glitch response during mode changes. While in these modes, with PMU Hi-Z, new x1 codes loaded to the FIN

DAC register and the Clamp DAC register will be calibrated, stored in x2 register and loaded directly to the DAC outputs.

FORCE1

FORCE0

Action

0

0

FV & Current Clamp (if clamp enabled)

0

1

FI & Voltage Clamp (if clamp enabled)

1

0

Hi-Z FOH Voltage (pre load FIN DAC & Clamp DAC)

1

1

Hi-Z FOH Current (pre load FIN DAC & Clamp DAC)

18

RESERVED

0

17

C2

16

C1

15

C0

Bits C2 through C0 address allow selection of the required current range.

C2

C1

C0

Action

0

0

0

±5µA current range

0

0

1

±20µA current range

0

1

0

±200µA current range

0

1

1

±2mA current range

1

0

0

±external current range

1

0

1

NOP

1

1

0

NOP

1

1

1

NOP