Nexperia

74LVC1G10

Single 3-input NAND gate

13. Abbreviations

Table 11. Abbreviations

Acronym

Description

CDM

Charged Device Model

CMOS

Complementary Metal Oxide Semiconductor

DUT

Device Under Test

ESD

ElectroStatic Discharge

HBM

Human Body Model

MM

Machine Model

TTL

Transistor-Transistor Logic

14. Revision history

Table 12. Revision history

Document ID

Release date Data sheet status

Change notice Supersedes

74LVC1G10 v.7

20220202

Product data sheet

-

74LVC1G10 v.6

Modifications:

• SOT363 (SC-88) package changed to SOT363-2 (TSSOP6) package.

74LVC1G10 v.6

20210602

Product data sheet

-

74LVC1G10 v.5

Modifications:

• The format of this data sheet has been redesigned to comply with the identity

guidelines of Nexperia.

• Legal texts have been adapted to the new company name where appropriate.

• Type number 74LVC1G10GF (SOT891 / XSON6) removed.

• Section 8: Derating values for Ptot total power dissipation updated.

• Fig. 10: Package outline drawing SOT457 (SC-74; TSOP6) updated.

74LVC1G10 v.5

20161128

Product data sheet

-

74LVC1G10 v.4

Modifications:

• Table 7: The maximum limits for leakage current and supply current have changed.

74LVC1G10 v.4

20140910

Product data sheet

-

74LVC1G10 v.3

Modifications:

• Package outline drawing of SOT886 (Fig. 11) modified.

74LVC1G10 v.3

20111208

Product data sheet

-

74LVC1G10 v.2

74LVC1G10 v.2

20101021

Product data sheet

-

74LVC1G10 v.1

74LVC1G10 v.1

20071002

Product data sheet

-

-

74LVC1G10

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© Nexperia B.V. 2022. All rights reserved

Product data sheet

Rev. 7 — 2 February 2022

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