April 1995

8

Philips Semiconductors

Product specification

P-channel enhancement mode vertical

D-MOS transistor

BSP204; BSP204A

PACKAGE OUTLINE

UNIT

A

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

EIAJ

mm

5.2

5.0

b

0.48

0.40

c

0.45

0.40

D

4.8

4.4

d

1.7

1.4

E

4.2

3.6

L

14.5

12.7

e

2.54

e1

1.27

L1

(1)

max

L2

max

2.5

2.5

b1

0.66

0.56

DIMENSIONS (mm are the original dimensions)

Notes

1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.

SOT54 variant

TO-92

SC-43

A

L

0

2.5

5 mm

scale

b

c

D

L1

d

E

Plastic single-ended leaded (through hole) package; 3 leads (on-circle)

SOT54 variant

1

2

3

L2

e1

e

97-04-14