AD9510-VCOSLASHPCB datasheet(38/60 Pages) AD

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AD9510

Rev. A | Page 38 of 60

Divider Phase Offset

The phase of each output may be selected, depending

on the divide ratio chosen. This is selected by writing the

appropriate values to the registers which set the phase and

start high/low bit for each output. These are the odd numbered

registers from 49h to 57h. Each divider has a 4-bit phase offset

<3:0> and a start high or low bit <4>.

Following a sync pulse, the phase offset word determines how

many fast clock (CLK1 or CLK2) cycles to wait before initiating

a clock output edge. The Start H/L bit determines if the divider

output starts low or high. By giving each divider a different

phase offset, output-to-output delays can be set in increments of

the fast clock period, tCLK.

Figure 39 shows four dividers, each set for DIV = 4, 50% duty

cycle. By incrementing the phase offset from 0 to 3, each output

is offset from the initial edge by a multiple of tCLK.

CLOCK INPUT

CLK

DIVIDER OUTPUTS

DIV = 4, DUTY = 50%

START = 0,

PHASE = 0

START = 0,

PHASE = 1

START = 0,

PHASE = 2

START = 0,

PHASE = 3

012

345

6789

10 11 12 13 14 15

tCLK

× t

CLK

× t

CLK

Figure 39. Phase Offset—All Dividers Set for DIV = 4, Phase Set from 0 to 3

For example:

CLK1 = 491.52 MHz

tCLK1 = 1/491.52 = 2.0345 ns

For DIV = 4

Phase Offset 0 = 0 ns

Phase Offset 1 = 2.0345 ns

Phase Offset 2 = 4.069 ns

Phase Offset 3 = 6.104 ns

The four outputs may also be described as:

OUT1 = 0°

OUT2 = 90°

OUT3 = 180°

OUT4 = 270°

Setting the phase offset to Phase = 4 results in the same relative

phase as the first channel, Phase = 0° or 360°.

In general, by combining the 4-bit phase offset and the Start

H/L bit, there are 32 possible phase offset states (see Table 18).

Table 18. Phase Offset—Start H/L Bit

49h to 57h

Phase Offset

(Fast Clock

Rising Edges)

Phase Offset <3:0>

Start H/L <4>

The resolution of the phase offset is set by the fast clock period

(tCLK) at CLK1 or CLK2. As a result, every divide ratio does not

have 32 unique phase offsets available. For any divide ratio, the

number of unique phase offsets is numerically equal to the

divide ratio (see Table 18):

DIV = 4

Unique Phase Offsets Are Phase = 0, 1, 2, 3

DIV= 7

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