AD9927BBCZ datasheet(29/100 Pages) AD

Il numero della parte	AD9927BBCZ

Spiegazioni elettronici	14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator

PDF	100 Pages

Scroll/Zoom	100%

Produttore elettronici	AD [Analog Devices]

Homepage	http://www.analog.com

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29 / 100 page

AD9927

Rev. 0 | Page 29 of 100

REGION 0: USE V-SEQUENCE 3

REGION 1: USE V-SEQUENCE 2

REGION 2: USE V-SEQUENCE 1

REGION 0: USE V-SEQUENCE 3

REGION 1: USE V-SEQUENCE 2

REGION 2: USE V-SEQUENCE 1

REGION 0: USE V-SEQUENCE 2

REGION 1: USE V-SEQUENCE 0

REGION 3: USE V-SEQUENCE 0

REGION 4: USE V-SEQUENCE 2

XV1

XV2

XV23

XV24

XV1

XV2

XV3

FIELD 0

FIELD1

FIELD2

REGION 2: USE V-SEQUENCE 3

FIELD0

FIELD1

FIELD2

FIELD3

FIELD4

FIELD5

FIELD1

FIELD4

FIELD2

XV3

XV23

XV24

VPAT0

XV1

XV2

XV23

XV24

XV3

XV1

XV2

XV23

XV24

XV3

XV1

XV2

XV23

XV24

XV3

VPAT1

CREATE THE VERTICAL PATTERN GROUPS,

UP TO FOUR TOGGLE POSITIONS FOR EACH OUTPUT.

BUILD THE V-SEQUENCES BY ADDING START POLARITY,

LINE START POSITION, NUMBER OF REPEATS, ALTERNATION,

GROUP A/B/C/D INFORMATION, AND HBLK/CLPOB PULSES.

V-SEQUENCE 0

(VPAT0, 1 REP)

V-SEQUENCE 1

(VPAT1, 2 REP)

V-SEQUENCE 2

(VPAT1, N REP)

BUILD EACH FIELD BY DIVIDING INTO DIFFERENT REGIONS

AND ASSIGNING A DIFFERENT V-SEQUENCE TO EACH

(MAXIMUM OF NINE REGIONS IN EACH FIELD).

USE THE MODE REGISTERS TO CONTROL WHICH FIELDS

ARE USED, AND IN WHAT ORDER (MAXIMUM OF SEVEN

FIELDS MAY BE COMBINED IN ANY ORDER).

Figure 34. Summary of Vertical Timing Generation

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