BST120 datasheet(4/12 Pages) PHILIPS

Il numero della parte	BST120

Spiegazioni elettronici	P-channel enhancement mode vertical D-MOS transistor

PDF	12 Pages

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Produttore elettronici	PHILIPS [NXP Semiconductors]

Homepage	http://www.nxp.com

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4 / 12 page

April 1995

Philips Semiconductors

Product speciﬁcation

P-channel enhancement mode vertical

D-MOS transistor

BST120

CHARACTERISTICS

Tj =25 °C unless otherwise speciﬁed

Drain-source breakdown voltage

−I

D =10 µA; VGS =0

−V(BR)DSS

min.

60 V

Drain-source leakage current

−VDS = 48 V; VGS =0

−IDSS

max.

µA

Gate-source leakage current

−VGS = 20 V; VDS =0

−IGSS

max.

100 nA

Gate threshold voltage

min.

max.

1.5

3.5

−ID = 1 mA; VDS =VGS

−VGS(th)

Drain-source ON-resistance

typ.

max.

4.5

Ω

−ID = 200 mA; −VGS = 10 V

RDS(on)

Transfer admittance

−I

D = 200 mA; −VDS = 15 V

 Yfs

typ.

200 mS

Input capacitance at f = 1 MHz

typ.

max.

−V

DS = 10 V; VGS =0

Ciss

Output capacitance at f = 1 MHz

typ.

max.

−VDS = 10 V; VGS =0

Coss

Feedback capacitance at f = 1 MHz

typ.

max.

−VDS = 10 V; VGS = 0

Crss

Switching times (see Figs 2 and 3)

ton

toff

typ.

−ID = 200 mA; −VDD = 50 V; −VGS = 0 to 10 V

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