LXT9785 datasheet(13/226 Pages) INTEL

13 / 226 page

Datasheet

Document Number: 249241

Revision Number: 007

Revision Date: August 28, 2003

Contents

Revision Number: 006 (INTERNAL RELEASE)

Revision Date: June 10, 2003

Page

Description

Changed "pseudo-ECL (PECL)" to "Low Voltage Positive Emitter Coupled Logic (LVPECL)" in the

second paragraph, front page.

Modified Table 5 “Intel® LXT9785/LXT9785E RMII Signal Descriptions – PQFP”. Added last

sentence to RXER0 through RXER7 signal description.

Modified Table 10 “Intel® LXT9785/LXT9785E Signal Detect – PQFP”.

Modified Table 11 “Intel® LXT9785/LXT9785E Network Interface Signal Descriptions – PQFP”,

Modified Table 13 “Intel® LXT9785/LXT9785E Miscellaneous Signal Descriptions – PQFP”. Added

note to PREASEL signal description.

116

Modified Section 4.1, “Introduction”. Changed "Pseudo-ECL (PECL)" to "Low Voltage PECL

(LVPECL)" in the first paragraph, second sentence.

119

Replace text under Section 4.2.1.3, “Fiber Interface”.

120

Modified Section 4.3.2, “Internal Loopback”.

130

Modified last sentence under Section 4.6.1.4, “Link Criteria”.

131

Modified text under Section 4.6.1.5, “Parallel Detection”. Added second paragraph.

136

Modified text under Section 4.7.4.3, “Receive Error”.

145

Changed "PECL" to "LVPECL in third paragraph, first sentence under Section 4.9.1, “100BASE-X

Network Operations”.

146

Modified Figure 28 “Intel® LXT9785/LXT9785E Protocol Sublayers”.

148

Modified Section 4.9.3.3, “Carrier Sense/Data Valid (RMII)”. Changed “asynchronously to

“synchronously.”

148

Modified text under Section 4.9.3.4, “Carrier Sense (SMII)”. Revised last sentence in first paragraph.

149

Modified paragraph under Section 4.9.3.6.3, “Polarity Correction”.

149

Replaced text under Section 4.9.3.7, “Fiber PMD Sublayer”.

150

Modified Section 4.10.1, “Preamble Handling”. Added text to last paragraph.

151

Modified first sentence under Section 4.10.4, “Jabber”.

152

Modified first paragraph of Section 4.11, “DTE Discovery Process”.

153

Modified Item 1 of Section 4.11.2, “Interaction between Processor, MAC, and PHY”.

158

Modified Section 4.12.3, “Out-of-Band Signaling”. Added sentence to end of first paragraph.

166

Replaced text under Section 5.2.5, “The Fiber Interface”.

170

Replaced Figure 36 “Recommended Intel® LXT9785/LXT9785E-to-3.3 V Fiber Transceiver

Interface Circuitry”.

171

Replaced Figure 37 “Recommended Intel® LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface

Circuitry”.

173

Modified Table 52 “Intel® LXT9785/LXT9785E Operating Conditions”.

174

Modified Table 53 “Intel® LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO =

2.5 V +/- 5%)”.

175

Modified Table 54 “Intel® LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO =

3.3 V +/- 5%)”.

175

Added Table 55 “Intel® LXT9785/LXT9785E Digital I/O DC Electrical Characteristics – SD Pins”.

176

Modified Table 58 “Intel® LXT9785/LXT9785E 100BASE-FX Transceiver Characteristics”.

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