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STSMIA832 Scheda tecnica(PDF) 5 Page - STMicroelectronics |
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STSMIA832 Scheda tecnica(HTML) 5 Page - STMicroelectronics |
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5 / 23 page ![]() STSMIA832 Pin configuration 5/23 2.1 Pin descriptions for reference: (D+, D-, STRB+, STRB-) Differential subLVDS data and strobe inputs to the receiver from the camera sensor interface. The signals operate at 150mV typical differential voltage levels and a common mode voltage of 900mV. The operating data rate is 650Mbps maximum. Depending on the CLASS_SEL pin selection mode, Data/Clock signaling or Data/Strobe signaling modes are activated. D1-D8, CLK STSMIA832 output data and clock lines. Parallel 8 bits of CMOS/LVTTL data is output at a maximum data rate of 82Mbps per line. Output LVTTL clock is transmitted in parallel with the data at 82MHz Max. SYNC-SEL The Horizontal Sync and Vertical Sync signals are extracted from the data stream before transmitting data on the parallel output D1-D8 if the device is working in ENABLED SYNC mode (SYNC_SEL = VL). If the device is working in DISABLED SYNC mode (SYNC_SEL = GND) the sync codes are not extracted from the data stream and the embedded Sync codes are transmitted along with the data on the parallel output. This allows for two modes of functioning, formatted and unformatted transmission of data on the data lines based on the selection by the Baseband processor. The main function table lists the functions for various combinations of SYNC_SEL pin and EN pin. CLASS-SEL The device embeds all functions forecast inside the SMIA Standard. STRB+ and STRB- signals are considered STROBE Signals when the device is working in HIGH CLASS mode (CLASS_SEL = VL). If the device is working in LOW CLASS mode (CLASS_SEL = GND) the STRB+ and STRB- inputs change their strobe functionality to CLOCK in order to be compliant with SMIA CLASS 0. In Class 0 mode of operation, data is read on the rising edge only. This allows for two modes of functioning, Clocked and Strobed transmission according to different applications and provides high flexibility to configure the final application in different Baseband processors. H-SYNC, V-SYNC In the ENABLED SYNC mode, the parallel data on D1-D8 is accompanied by the Horizontal and Vertical Sync signals on the H-SYNC and V-SYNC pins and together they are used to reconstruct the image frame. The H-SYNC and V-SYNC are generated by extracting the SMIA 32-bit Synchronization codes (SOF, EOF, SOL, EOL) on the serial input data stream. EN Enable pin is to enable the Power-Down Mode. This mode enables the shutting down of the device when the interface is not in use. The maximum current consumption can be reduced to 10 µA. This provision makes this device suitable for portable applications like Mobile phones or Portable Battery Equipment. |
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