56F8037 datasheet(39/180 Pages) FREESCALE

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Features

56F8037 Data Sheet, Rev. 2

Freescale Semiconductor

Preliminary

3.2 Features

The OCCS module interfaces to the oscillator and PLL and offers these features:

•

Internal relaxation oscillator

•

Ability to power down the internal relaxation oscillator or crystal oscillator

•

Ability to put the internal relaxation oscillator into Standby mode

•

3-bit postscaler provides control for the PLL output

•

Ability to power down the PLL

•

Provides a 2X system clock which operates at twice the system clock to the System Integration Module

(SIM)

•

Provides a 3X system clock which operates at three times the system clock to PWM and Timer modules

•

Safety shutdown feature is available if the PLL reference clock is lost

•

Can be driven from an external clock source

The clock generation module provides the programming interface for the PLL, internal relaxation

oscillator, and crystal oscillator.

3.3 Operating Modes

In 56F8000 family devices, an internal oscillator, an external crystal, or an external clock source can be

used to provide a reference clock to the SIM.

The 2X system clock source output from the OCCS can be described by one of the following equations:

2X system frequency = oscillator frequency

2X system frequency = (oscillator frequency x 8) / (postscaler)

where:

postscaler = 1, 2, 4, 8, 16, or 32

The SIM is responsible for further dividing these frequencies by two, which will insure a 50% duty cycle

in the system clock output.

The 56F8000 family devices’ on-chip clock synthesis module has the following registers:

•

Control Register (OCCS_CTRL)

•

Divide-by Register (OCCS_DIVBY)

•

Status Register (OCCS_STAT)

•

Shutdown Register (OCCS_SHUTDN)

•

Oscillator Control Register (OCCS_OCTRL)

For more information on these registers, please refer to the 56F802x and 56F803x Peripheral Reference

Manual.

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