COM20020D datasheet(68/72 Pages) SMSC

68 / 72 page

CKP3-1 may cause spike noise to appear on the

output clock line.

Setting the EF bit will include flip-flops inserted

between the Configuration register and Pre-

Scalar for synchronizing the CKP3-1 with Pre-

Scalar’s internal clocks.

Never change the CKP3-1 when the data rate is

over 5 Mbps. They must all be zero.

C) Shorten The Write Interval Time To The

Command Register

The COM20020D limits the write interval time for

continuous writing to the Command register. The

minimum interval time is changed by the Data

Rate. It's 100 nS at the 2.5 Mbps and 1.6

µS at

the 156.25 Kbps. This 1.6

µS is very long for

CPU.

Setting the EF bit will change the clock source

from OSCK clock (8 times frequency of data

rate) to XTAL clock which is not changed by the

data rate, such that the minimum interval time

becomes 100 nS.

D) Eliminate The Write Prohibition Period For

The Enable Tx/Rx Commands

The COM20020D has a write prohibition period

for

writing

the

Enable

Transmit/Receive

Commands. This period is started by the TA or

RI bit (Status Reg.) returning to High. This

prohibition period is caused by setting the TA/RI

bit with a pulse signal.

It is 3.2

µS at 156.25

Kbps. This period may be a problem when using

interrupt processing. The interrupt occurrs when

the RI bit returns to High. The CPU writes the

next Enable Receive Command to the other

page immediately. In this case, the interval time

between the interrupt and writing Command is

shorter than 3.2

µS.

Setting the EF bit will cause the TA/RI bit to

return to High upon release of the pulse signal

for setting the TA/RI bit, instead of at the start of

the pulse. This is illustrated in figure 25 on the

following page.

COM20020D Scheda tecnica(PDF) 68 Page - SMSC Corporation

COM20020D Scheda tecnica(HTML) 68 Page - SMSC Corporation

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