 |
Motore di ricerca datesheet componenti elettronici |
|
|
Motore di ricerca datesheet componenti elettronici |
|
S5935QF Scheda tecnica(PDF) 39 Page - Applied Micro Circuits Corporation |
|
|
|||||||||||||||||||||||||||||
S5935QF Scheda tecnica(HTML) 39 Page - Applied Micro Circuits Corporation |
|
|
39 / 190 page  3-31 PCI CONFIGURATION REGISTERS S5935 LATENCY TIMER REGISTER (LAT) Register Name: Latency Timer Address Offset: 0Dh Power-up value: 00h Boot-load: External nvRAM offset 04Dh Attribute: Read/Write, bits 7:3; Read Only bits 2:0 Size: 8 bits The latency timer register has meaning only when this controller is used as a bus master and pertains to the number of PCI bus clocks that this master will be guaranteed. The nonzero value for this register is internally decremented after this device has been granted the bus and has begun to assert FRAME#. Prior to this latency timer count reaching zero, this device can ignore the removal of the bus grant and may continue the use of the bus for data transfers. 7 0 Latency Timer value (R/W) # of clocks x 8 0 1 0 2 0 3 X 4 X 5 X 6 X X Bit Value Figure 8. Latency Timer Register |
|
Link URL |
| Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | Collegamento alla scheda tecnica | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Italian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
