SC1486 datasheet(13/17 Pages) SEMTECH

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 2002 Semtech Corp.

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SC1486

POWER MANAGEMENT

SC1486 System DC Accuracy (VTT Controller)

Two IC parameters effect system DC accuracy, the error

comparator offset voltage, and the switching frequency

variation with line and load. The 1486 regulates to the

REFOUT voltage not the REFIN voltage. Since DDR

specifications are written with respect to REFOUT, the

offset of the reference buffer does not create a regulation

error.

The error comparator offset is trimmed so that it trips

when VOUT is 1.25 volts at room temperature. This offset

does not drift significantly with supply and temperature.

Thus, the error comparator contributes 1% or less to DC

system inaccuracy.

The on pulse in the SC1486 is calculated to give a pseudo

fixed frequency. Nevertheless, some frequency variation

with line and load can be expected. This variation changes

the output ripple voltage. Because constant on regulators

regulate to the valley of the output ripple, ½ of the output

ripple appears as a DC regulation error. For example, if

REFOUT=1.25 volts, then the valley of the output ripple

will be 1.25 volts. If the ripple is 20mv with VIN=6, then

the DC output voltage will be 1.26 volts. If the ripple is

40mv with VIN=25 volts, then the DC output voltage will

be 1.27 volts. The best way to minimize this effect is to

minimize the output ripple.

To compensate for valley regulation is usually desirable

to use passive droop. Take the feedback directly from

the output side of the inductor incorporating a small

amount of trace resistance between the inductor and

output capacitor. This trace resistance should be

optimized so that at full load the output droops to near

the lower regulation limit. Passive droop minimizes the

required output capacitance because the voltage

excursions due to load steps are reduced. Passive droops

also improves stability so it should be used when possible.

1486 System DC Accuracy (VVDQ Controller)

Three IC parameters affect system DC accuracy, the

internal band gap reference, the error comparator offset

voltage, and the switching frequency variation with line

and load.

The internal 1% 1.5V reference contains two error

components, a 0.5% DC error and a 0.5% supply and

temperature error. The error comparator offset is

trimmed so that it trips when the feedback pin is nominally

0.5 volts +/-1% at room temperature. The comparator

offset trim compensates for any DC error in the reference.

Thus, the percentage error is the sum of the reference

variation over supply and temperature and the offset in

the error comparator or 1.5%.

The on pulse in the SC1486 is calculated to give a pseudo

fixed frequency. Nevertheless, some frequency variation

with line and load can be expected. This variation changes

the output ripple voltage. Because constant on regulators

regulate to the valley of the output ripple, ½ of the output

ripple appears as a DC regulation error. For example, if

the feedback resistors are chosen to divide down the

output by a factor of five, the valley of the output ripple

will be 2.5V. If the ripple is 50mv with VIN = 6 volts, then

the measured DC output will be 2.525 volts. If the ripple

increases to 80mv with VIN = 25 volts, then the

measured DC output will be 2.540. The best way to

minimize this effect is to minimize the output ripple.

To compensate for valley regulation is usually desirable

to use passive droop. Take the feedback directly from

the output side of the inductor incorporating a small

amount of trace resistance between the inductor and

output capacitor. This trace resistance should be

optimized so that at full load the output droops to near

the lower regulation limit. Passive droop minimizes the

required output capacitance because the voltage

excursions due to load steps are reduced.

Board components and layout also influence DC

accuracy. The use of 1% feedback resistors contribute

1%. If tighter DC accuracy is required use 0.1% feedback

resistors.

The output inductor value may change with current. This

will change the output ripple and thus the DC output

voltage.It will not change the frequency.

Switching frequency variation with load can be minimized

by choosing lower RDSON MOSFETs. High RDSON

MOSFETS will cause the switching frequency to increase

as the load current increases. This will reduce the ripple

and thus the DC output voltage. This inherent droop

should be considered when deciding if passive droop is

required. If the output ripple some passive droop may

be desirable to further reduce the output capacitance.

Application Information (Cont.)

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