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VT8363A Scheda tecnica(PDF) 7 Page - List of Unclassifed Manufacturers

Il numero della parte VT8363A
Spiegazioni elettronici  KT133A AMD ATHLON??NORTH BRIDGE
PDF  54 Pages
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Produttore elettronici  ETC2 [List of Unclassifed Manufacturers]
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VT8363A Scheda tecnica(HTML) 7 Page - List of Unclassifed Manufacturers

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KT133A - VT8363A
Preliminary Revision 0.1, October 9, 2000
-1-
Features
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VIA VT8363A
KT133A AMD ATHLON™ NORTH BRIDGE
Single-Chip North Bridge
for Socket-A (Socket-462) Based Athlon CPUs
with 200 / 266 MHz Front Side Bus
for Desktop PC Systems
with AGP 4x and PCI
plus Advanced Memory Controller
supporting PC133 / PC100 SDRAM and VCM
• High Performance and High Integration Athlon AGP 4x / PC133 Chipset with Advanced System
Power Management
KT133A Chipset: VT8363A system controller and VT82C686A PCI to ISA bridge
Single chip Athlon system controller with 64-bit Socket-A Athlon CPU, 64-bit system memory, 32-bit PCI and 32-
bit AGP interfaces
PCI-to-ISA bridge chip includes UltraDMA-33/66 EIDE, 4 USB Ports, Integrated Super-I/O, AC97 / MC97 link (for
Audio and Modem support), Hardware Monitoring, Power Management, and Keyboard / PS2-Mouse Interfaces plus
RTC / CMOS on chip
Supports separately powered 3.3V (5V tolerant) interface to system memory, AGP, and PCI bus
Modular power management and clock control for advanced system power management
• High Performance Athlon CPU Interface
Supports Socket-A (Socket-462) AMD Athlon processors with 200 and 266 MHz Front Side Bus
HSTL-like 1.5V high-speed transceiver logic signal levels
Independent address, data, and snoop interfaces
100 and 133 MHz DDR (Double Data Rate) transfer on Athlon CPU address and data buses
Built-in PLL (Phase Lock Loop) circuitry for optimal skew control within and between clocking regions
Four-entry command queue to accommodate maximum CPU throughput
Four-entry probe queue to stores probes from the system to the processor
Twenty four-entry processor system data and control queue to store system data control commands in two separate
read and write buffers for data movement in and out of processor interface
Supports WC (Write Combining) cycles
Sleep mode support
System management interrupt, memory remap and STPCLK mechanism



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