MCP621 datasheet(22/68 Pages) MICROCHIP

22 / 68 page

MCP621/1S/2/3/4/5/9

DS20002188E-page 22

 2009-2021 Microchip Technology Inc. and its subsidiaries

4.0

APPLICATIONS

The MCP621/1S/2/3/4/5/9 family of self-zeroed op

amps is manufactured using Microchip’s state-of-the-

art CMOS process. It is designed for low-cost, low-

power and high-precision applications. Its low supply

voltage, low quiescent current and wide bandwidth

makes the MCP621/1S/2/3/4/5/9 ideal for battery-

powered applications.

4.1

Calibration and Chip Select

These op amps include circuitry for dynamic calibration

of the offset voltage (VOS).

4.1.1

mCal CALIBRATION CIRCUITRY

The internal mCal circuitry, when activated, starts a

delay timer (to wait for the op amp to settle to its new

bias point), then calibrates the input offset voltage

(VOS). The mCal circuitry is triggered at power-up (and

after some power brown-out events) by the internal

POR, and by the memory’s parity detector. The

power-up time, when the mCal circuitry triggers the

calibration sequence, is 200 ms (typical).

4.1.2

CAL/CS PIN

The CAL/CS pin gives the user a means to externally

demand a Low-Power mode of operation, then to

calibrate VOS. Using the CAL/CS pin makes it possible

to correct VOS as it drifts over time (1/f noise and aging;

see Figure 2-35) and across temperature.

The CAL/CS pin performs two functions: it places the

op amp(s) in a Low-Power mode when it is held high,

and starts a calibration event (correction of VOS) after a

rising edge.

While in the Low-Power mode, the quiescent current is

quite small (ISS = -3 µA, typical). The output is also in a

High Z state.

During the calibration event, the quiescent current is

near, but smaller than, the specified quiescent current

(2.5 mA, typical). The output continues in the High Z

state, and the inputs are disconnected from the

external circuit, to prevent internal signals from

affecting circuit operation. The op amp inputs are

internally connected to a Common mode voltage buffer

and feedback resistors. The offset is corrected (using a

digital state machine, logic and memory), and the

calibration constants are stored in memory.

Once the calibration event is completed, the amplifier is

reconnected to the external circuitry. The turn-on time,

when calibration is started with the CAL/CS pin, is 5 ms

(typical).

There is an internal 5 M

 pull-down resistor tied to the

CAL/CS pin. If the CAL/CS pin is left floating, the

amplifier operates normally.

For the MCP625 dual and the MCP629 quad, there is

an additional constraint on toggling the two CAL/CS

pins close together; see the tCON specification in

Table 1-3. If the two pins are toggled simultaneously, or

if they are toggled separately with an adequate delay

between them (greater than tCON), then the CAL/CS

inputs are accepted as valid. If one of the two pins

toggles, while the other pin’s calibration routine is in

progress, then an invalid input occurs and the result is

unpredictable.

4.1.3

INTERNAL POR

This part includes an internal Power-on Reset (POR) to

protect the internal calibration memory cells. The POR

monitors the power supply voltage (VDD). When the

POR detects a low VDD event, it places the part into the

Low-Power mode of operation. When the POR detects

a normal VDD event, it starts a delay counter, then

triggers a calibration event. The additional delay gives

a total POR turn-on time of 200 ms (typical); this is also

the power-up time (since the POR is triggered at power

up).

4.1.4

PARITY DETECTOR

A parity error detector monitors the memory contents

for any corruption. In the rare event that a parity error is

detected (e.g., corruption from an alpha particle), a

POR event is automatically triggered. This will cause

the input offset voltage to be recorrected, and the op

amp will not return to normal operation for a period of

time (the POR turn-on time, tPON).

4.1.5

CALIBRATION INPUT PIN

A VCAL pin is available in some options (e.g., the single

MCP621) for those applications that need the

calibration to occur at an internally driven Common

mode voltage other than VDD/3.

Figure 4-1 shows the reference circuit that internally

sets the op amp’s Common mode reference voltage

(VCM_INT) during calibration (the resistors are

disconnected from the supplies at other times). The

 resistor provides overcurrent protection for the

buffer.

FIGURE 4-1:

Common-Mode Reference’s

Input Circuitry.

To op amp during

VCAL

BUFFER



300 k



150 k



VSS

VDD

calibration

VCM_INT

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