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MCP621ST-E/OT Scheda tecnica(PDF) 6 Page - Microchip Technology |
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MCP621ST-E/OT Scheda tecnica(HTML) 6 Page - Microchip Technology |
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6 / 68 page ![]() MCP621/1S/2/3/4/5/9 DS20002188E-page 6 2009-2021 Microchip Technology Inc. and its subsidiaries 1.3 Timing Diagram FIGURE 1-1: Timing Diagram. TABLE 1-4: TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +2.5V to +5.5V,VSS = GND. Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges Specified Temperature Range TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C (Note 1) Storage Temperature Range TA -65 — +150 °C Thermal Package Resistances Thermal Resistance, 5L-SOT-23 θJA — 220.7 — °C/W Thermal Resistance, 6L-SOT-23 θJA — 190.5 — °C/W Thermal Resistance, 8L-2x3 TDFN θJA —52.5 — °C/W Thermal Resistance, 8L-3x3 DFN θJA —56.7 — °C/W (Note 2) Thermal Resistance, 8L-SOIC θJA — 149.5 — °C/W Thermal Resistance, 10L-3x3 DFN θJA —53.3 — °C/W (Note 2) Thermal Resistance, 10L-MSOP θJA —202 — °C/W Thermal Resistance, 14L-SOIC θJA —95.3 — °C/W Thermal Resistance, 14L-TSSOP θJA —100 — °C/W Thermal Resistance, 16L-4x4-QFN θJA —45.7 — °C/W (Note 2) Note 1: Operation must not cause TJ to exceed the Maximum Junction Temperature specification (150°C). 2: Measured on a standard JC51-7, four-layer printed circuit board with ground plane and vias. High Z VDD VOUT -3 µA (typical) High Z ISS ICS -3 µA (typical) -2.5 mA (typical) VPRH VPRL tPON tPOFF On 0nA (typical) High Z -3 µA (typical) -2.5 mA (typical) tCOFF tCON On 0.7 µA (typical) 0nA (typical) CAL/CS VIH VIL tCSU Note: For the MCP625 dual and the MCP629 quad, there is an additional constraint on toggling the two CAL/CS pins close together; see the TCON specification in Table 1-3. |
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