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UPD75P4308GS Scheda tecnica(PDF) 32 Page - Renesas Technology Corp

Il numero della parte UPD75P4308GS
Spiegazioni elettronici  MOS INTEGRATED CIRCUIT
PDF  61 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD75P4308GS Scheda tecnica(HTML) 32 Page - Renesas Technology Corp

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µPD75P4308
30
Data Sheet U10909EJ2V1DS
8.3 Program Memory Read Procedure
The
µPD75P4308 can read out the program memory contents via the following steps.
(1)
Pull down unused pins to VSS via resistors. Set the X1 pin to low.
(2)
Apply +5 V to the VDD and VPP pins.
(3)
Wait 10
µs.
(4)
Zero-clear mode for program memory addresses.
(5)
Apply +6 V to VDD and +12.5 V to VPP.
(6)
Verify mode. When a clock pulse is input to the X1 pin, data is output sequentially to one address at a
time based on a cycle of four pulse inputs.
(7)
Zero-clear mode for program memory addresses.
(8)
Apply +5 V to the VDD and VPP pins.
(9)
Power supply OFF
The following diagram illustrates steps (2) to (7).
VPP
VDD
VDD + 1
VDD
VDD
X1
D0/P60/KR0-
D3/P63/KR3
D4/P50-
D7/P53
Data output
Data output
MD0/P30
MD2/P32
MD3/P33
MD1/P31
“L”
VPP



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