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TAS5036B Scheda tecnica(PDF) 17 Page - Texas Instruments

Il numero della parte TAS5036B
Spiegazioni elettronici  Six Channel Digital Audio PWM Precessor
PDF  56 Pages
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Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
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TAS5036B Scheda tecnica(HTML) 17 Page - Texas Instruments

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Architecture Overview
11
SLES073—February 2003
TAS5036B
Table 2–5. Supported Word Lengths
DATA MODES
WORD
LENGTHS
MOD2
MOD1
MOD0
Right justified, MSB first
16
0
0
0
Right justified, MSB first
20
0
0
1
Right justified, MSB first
24
0
1
0
I2S
16
0
1
1
I2S
20
1
0
0
I2S
24
1
0
1
Left justified, MSB first
24
1
1
0
DSP frame
16
1
1
1
2.1.7.1
I2S Timing
I2S timing uses an LRCLK to define when the data being transmitted is for the left channel or the right channel.
The LRCLK is low for the left channel and high for the right channel. A bit clock running at 48 or 64 times Fs
is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state
to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of the bit
clock. The TAS5036B masks unused trailing data bit positions. Master mode only supports a 64 times Fs bit
clock.
23
22
SCLK
32 Clks
LRCLK (Note Reversed Phase)
Left Channel
24-Bit Mode
9
8
5
4
1
0
19
18
20-Bit Mode
5
4
1
0
16-Bit Mode
1
0
15
14
MSB
LSB
23
22
SCLK
32 Clks
Right Channel
9
8
5
4
1
0
19
18
5
4
1
0
1
0
15
14
MSB
LSB
2-Channel I2S (Philips Format) Stereo Input
Figure 2–3. I2S 64-Fs Format



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