PC7447AMGH1000LB datasheet(19/44 Pages) ATMEL

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5387B–HIREL–07/05

PC7447A [Preliminary]

6.4.4.6

Minimum Core Frequency Requirements with DFS

In many systems, enabling DFS can result in very low processor core frequencies. However,

care must be taken to ensure that the resulting processor core frequency is within the limits

specified in Table 9-2 on page 25. Proper operation of the device is not guaranteed at core fre-

quencies below the specified minimum f

core.

6.4.5

Power Consumption

Table 7 provides the power consumption for the PC7447A. For information regarding power

consumption when dynamic frequency switching is enabled, See “Dynamic Frequency Switch-

ing (DFS)” on page 17..

Notes:

These values apply for all valid processor buses. The values do not include I/O supply power (OVDD) or PLL supply power

(AVDD). OVDD power is system dependent but is typically < 5% of V

DD power. Worst case power consumption for AVDD <

3mW.

Typical power is an average value measured at the nominal recommended V

DD (see Table 6-2 on page 10) and 65°C while

running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz

3. Maximum power is the average measured at nominal V

DD and maximum operating junction temperature (see Table 6-2 on

page 10) while running an entirely cache-resident, contrived sequence of instructions which keep all the execution units

maximally busy.

4. Doze mode is not a user-definable state; it is an intermediate state between full-power and either nap or sleep mode. As a

result, power consumption for this mode is not tested.

5. Power consumption for these devices is artificially constrained during screening to assure lower power consumption than

other speed grades.

Table 6-6.

Power Consumption for PC7447A

Processor (CPU) Frequency

1000

1167

1267

1333(5)

1420

Unit

Full-Power Mode

Core Power Supply

1.1

1.3

Typical(1)(2)

9.2

18.3

Maximum(1)(3)

Nap Mode

11.5

Typical(1)(2)

1.3

4.1

3.3

4.1

Sleep Mode

Typical(1)(2)

1.3

4.1

3.3

4.1

Deep Sleep Mode (PLL Disabled)

Typical(1)(2)

1.2

3.2

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