MP86934 – 16V INTELLI-PHASE SOLUTION IN TQFN 3X4

MP86934 Rev.1.2

www.MonolithicPower.com

13

5/26/2021

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APPLICATION INFORMATION

PCB Layout Guidelines

PCB layout plays an important role to achieve

stable operation. For optimal performance,

follow these guidelines.

1. Place the input MLCC capacitors as close to

the VIN and PGND pins as possible. The

major MLCC capacitors should be placed

on the same layer as MP86934. Maximize

the VIN and PGND copper plane to

minimize the parasitic impedance.

2. Place PGND Vias as many as possible and

close to the pin to minimize both parasitic

impedance and thermal resistance.

3. Place VCC decoupling capacitor close to

the device. Connect AGND and PGND at

the point of VCC capacitor's ground

connection.

4. Place BST capacitor as close to the BST

and SW pins as possible. Use trace width of

20 mils or higher to route the path. It is

recommended

to

use

0.1µF

to

1µF

bootstrap capacitor.

5. Keep the CS signal trace away from high

current

path

like

SW

and

PWM.

EXAMPLE OF PCB LAYOUT (PLACEMENT & TOP LAYER PCB).

Input Capacitor: 0805 & 0402 package (top side) & 0603 package (bottom side)

Inductor: 6.5 x 6.5 (mm)

VCC/BST capacitor: 0402 package

Via size: 20/10 mils