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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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UPD17062 Scheda tecnica(PDF) 77 Page - Renesas Technology Corp |
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UPD17062 Scheda tecnica(HTML) 77 Page - Renesas Technology Corp |
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77 / 298 page  75 µPD17062 b3 b2 b1 b0 0 IDCDMAEN 00 00H 0 1 DMA prohibited mode (instruction cycle = 2 s) DMA mode (instruction cycle = 12 s) µ µ 9.1 IDCDMAEN (00H, b1) This flag must be set to enable the operation of IDC. When the IDCDMAEN flag is set, the mode changes to DMA mode and IDC is enabled. In DMA mode, the instruction cycle is seen as 12 µs. For details, see Chapter 20. 9.2 SP (01H) SP is a pointer that addresses the stack register. b3 b2 b1 b0 0 (SPb2) (SPb0) 01H 0 0 0 0 0 1 01 0 01 1 10 0 10 1 11 0 11 1 (SPb1) Level 6 Level 5 Level 4 Level 3 Level 2 Level 1 At reset Not to be set SP (stack pointer) |
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