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UPD17072 Scheda tecnica(PDF) 82 Page - Renesas Technology Corp

Il numero della parte UPD17072
Spiegazioni elettronici  MOS INTEGRATED CIRCUIT
PDF  228 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD17072 Scheda tecnica(HTML) 82 Page - Renesas Technology Corp

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µPD17072,17073
80
Figure 11-10. Configuration of Interrupt Edge Select Register
Note
For the function of the BTM1CK flag, refer to 12.3.1 Outline of basic timer 1.
Note that as soon as the interrupt request issuing edge is changed by the IEG flag, the interrupt request signal
may be issued.
Suppose that the IEG flag is set to “1” (specifying the falling edge) and that a high level is input to the INT pin, as
shown in Table 11-2. If the IEG flag is cleared at this time, the edge detector circuit judges that a rising edge has
been input, and issues an interrupt request.
Flag symbol
b3
0
b2
I
N
T
b1
B
T
M
1
C
K
b0
I
E
G
Name
Address
(BANK1)
56H
Read/
Write
R/W
Sets input edge to issue interrupt request of INT pin
Rising edge
Falling edge
0
1
Sets time interval at which IRQBTM1 flag is setNote
32 ms (31.25 Hz)
8 ms (125 Hz)
0
1
Detects status of INT pin
Low level is input to INT pin
High level is input to INT pin
0
1
Fixed to “0”
Power-ON
Clock stop
CE
0
0
0
0
0
0
0
0
0
0
Interrupt edge select
register
At
reset



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