UPD17708 datasheet(91/358 Pages) RENESAS

91 / 358 page

µPD17704, 17705, 17707, 17708, 17709

Table 9-1. Relationships between Peripheral Hardware and Data Buffer (2/2)

At Reset

Clock

Function

Power-ON WDT&SP

Stop

reset

0Note

Sets compare voltage VADCREF of A/D converter

Undefined Undefined Undefined Undefined

Sets serial-out data and reads serial-in data

Retained

Sets modulo register value of timer 0

Retained

Reads count value of timer 0 counter

Retained

Sets modulo register value of timer 1

Retained

Reads count value of timer 1 counter

Retained

Sets modulo register value of timer 2

Retained

Reads count value of timer 2 counter

000

Retained

Transfers data with address register

Undefined Undefined Retained

Retained

Saves data of data buffer

Undefined Undefined Retained

Retained

Sets division value (N value) of PLL

0000

Reads count value of frequency counter

1FF

Retained

1FF

Sets duty of output signal of D/A converter

Sets duty of output signal of D/A converter (multiplexed with modulo register of timer 3)

Sets modulo register value of timer 3

Note

Value in hardare mode. “Retained” in software mode.

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