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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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UPD17708 Scheda tecnica(PDF) 227 Page - Renesas Technology Corp |
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UPD17708 Scheda tecnica(HTML) 227 Page - Renesas Technology Corp |
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227 / 358 page  225 µPD17704, 17705, 17707, 17708, 17709 16.2.6 Wait control block and acknowledge control block The wait control block keeps communication waiting or releases communication from the wait status. The condition under which communication is kept waiting is set by the SIO0WRQ0 and 1 flags (bits 0 and 1 of serial I/O0 wait control register). Serial communication is started when the SIO0NWT flag (bit 2 of serial I/O0 wait control register) is set (released from the wait status). The communication status can be detected by the SIO0NWT flag. When “0” is written to the SIO0NWT flag while communication is released from the wait status, the wait status is set. This is called forced wait status. The acknowledge control block outputs and detects an acknowledge signal in the I2C bus mode. An acknowledge signal is set and read by the SBACK flag (bit 3 of serial I/O0 wait control register). Figure 16-7 shows the configuration of the serial I/O0 wait control register. Figure 16-8 shows the configuration of the serial I/O0 wait status judge register. |
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