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UPD17708 Scheda tecnica(PDF) 233 Page - Renesas Technology Corp |
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UPD17708 Scheda tecnica(HTML) 233 Page - Renesas Technology Corp |
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233 / 358 page ![]() 231 µPD17704, 17705, 17707, 17708, 17709 This is because, even if only the SBACK flag is set, the SIO0NWT flag is also set because it is in the register at the same address. If the wait status is set at this time, the wait status is released and one pulse of the shift clock is output. Figure 16-11. Acknowledge Output and Input Operations Data input Data Hi-Z (D1) Hi-Z (D0) SBACK output Hi-Z Shift clock 7 8 9 Acknowledge output At this time, wait status must be released at the same time. Data output Data D1 output D0 output ACK at reception side Shift clock 7 8 9 Acknowledge input (a) During reception (b) During transmission |
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