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UPD17708 Scheda tecnica(PDF) 246 Page - Renesas Technology Corp

Il numero della parte UPD17708
Spiegazioni elettronici  MOS INTEGRATED CIRCUIT
PDF  358 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD17708 Scheda tecnica(HTML) 246 Page - Renesas Technology Corp

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µPD17704, 17705, 17707, 17708, 17709
16.2.12 Status of serial interface 0 at reset
(1) At power-ON reset
Each pin is set in the general-purpose input port mode.
The contents of presettable shift register 0 are undefined.
(2) At WDT&SP reset
Each pin is set in the general-purpose input port mode.
The contents of presettable shift register 0 are undefined.
(3) On execution of clock stop instruction
Each pin is set in the general-purpose I/O port mode and remains in the previous input or output mode.
The contents of presettable shift register 0 are undefined.
(4) At CE reset
Each pin is set in the general-purpose I/O port mode and remains in the previous input or output mode.
The contents of presettable shift register 0 are undefined.
(5) In halt status
Each pin retains its set status.
Output of the internal clock is stopped in the status where the HALT instruction is executed.
When an external clock is used, the operation continues even if the HALT instruction is executed.
Presettable shift register 0 retains the previous value.



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