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CST12.0MTWA Scheda tecnica(PDF) 28 Page - STMicroelectronics

Il numero della parte CST12.0MTWA
Spiegazioni elettronici  8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
PDF  153 Pages
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Produttore elettronici  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

CST12.0MTWA Scheda tecnica(HTML) 28 Page - STMicroelectronics

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9.2 RESET SEQUENCE MANAGER (RSM)
9.2.1 Introduction
The reset sequence manager includes three RE-
SET sources as shown in Figure 15:
s
External RESET source pulse
s
Internal LVD RESET (Low Voltage Detection)
s
Internal WATCHDOG RESET
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in Figure 14:
s
Delay depending on the RESET source
s
4096 CPU clock cycle delay
s
RESET vector fetch
The 4096 CPU clock cycle delay allows the oscil-
lator to stabilise and ensures that recovery has
taken place from the Reset state.
The RESET vector fetch phase duration is 2 clock
cycles.
Figure 14. RESET Sequence Phases
Figure 15. Reset Block Diagram
RESET
DELAY
INTERNAL RESET
4096 CLOCK CYCLES
FETCH
VECTOR
fCPU
RESET
RON
VDD
WATCHDOG RESET
LVD RESET
INTERNAL
RESET



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