DA9316.003

March 23, 2005

5

DATA

LATCH

OUTPU T

t1 = Data Setup Time (80ns)

t2 = Strobe W idth (80ns)

t3 = Settling Time (2us typical)

t1

t1

t2

t2

t3

AC PERFORMANCE CHARACTERISTICS

These characteristics are included for design guidance only and are subject to sample testing only. VDD=+15V,

VREF=10V, IO1=IO2=DGND=0V except where stated. Output Amp is HOS-050.

(test conditions Ta=+25C)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Propagation Delay

IO1 load R=100Ω, Cext=13pF

All Data Inputs 0V to VDD or

VDD to 0V

From 50% digital input change

to 90% of final analog output.

300

ns

CURRENT SETTLING

Major Code Transition

Full Scale Transition

ts

TIMESettling

to +0.01% FSR (strobed).

0111111111111111 to

1000000000000000 or

1000000000000000 to

0111111111111111

All Data Inputs 0V to VDD or

VDD to 0V

1.5

3.0

µS

µs

OUTPUT CAPACITANCE

CIO1 (Pin 16)170

CIO2 (Pin 15)

CIO1 (Pin 16)

CIO2 (Pin 15)

Co

Digital inputs VIH

Digital inputs VIH

Digital inputs VIL

Digital inputs VIL

170

30

80

100

pF

pF

pF

pF

Digital to Analog Glitch

Energy

Q

VREF =0V

DAC register alternately loaded

with all 0s and all 1s

250

nVs

Multiplying Feedthrough

Error at IO1

FT

VREF=20Vpp; f=10kHz sine wave

VREF=20Vpp, f=1kHz sine wave

3.0

0.3

mVpp

mVpp

Power Supply Rejection

Ratio

PSRR

VDD = 14 to 16V

±0.0001

±0.002

%/%

TIMING DIAGRAM