AM69 datasheet(3/300 Pages) TI1

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3 Description

The AM69 scalable processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart

Vision Camera applications and built on extensive market knowledge accumulated over a decade of TI’s

leadership in the Vision processor market. The AM69x family is built for a broad set of cost-sensitive high-

performance compute applications in Factory Automation, Building Automation, and other markets.

The AM69 provides high performance compute technology for both traditional and deep learning algorithms

at industry leading power/performance ratios with a high level of system integration to enable scalability and

lower costs for advanced vision camera applications. Key cores include the latest Arm and GPU processors for

general compute, next generation DSP with scalar and vector cores, dedicated deep learning and traditional

algorithm accelerators, an integrated next generation imaging subsystem (ISP), video codec, and isolated MCU

island. All protected by industrial-grade safety and security hardware accelerators.

General Compute Cores and Integration Overview: Two quad-core cluster configurations (8 cores total)

of Arm® Cortex®-A72 facilitate multi-OS applications with minimal need for a software hypervisor. Up to two

Dual-core (4 cores total) Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to

leave the Arm® Cortex®-A72 core’s unencumbered for applications. Building on the existing world-class ISP,

TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and

features targeting analytics applications. Integrated diagnostics and safety features support operations up to

SIL-2 levels while the integrated security features protect data against modern day attacks. CSI2.0 ports enable

multi sensor inputs.

Key Performance Cores Overview: The C7000™ DSP next generation core (“C7x”) combines TI’s industry

leading DSP and EVE cores into a single higher performance core and adds floating-point vector calculation

capabilities, enabling backward compatibility for legacy code while simplifying software programming. Four

“MMA” deep learning accelerators enable performance up to 32 Trillion Operations Per Second (TOPS) [8 TOPS

per core] within the lowest power envelope in the industry, even when operating even at the worst case junction

temperatures of 105°C and 125°C. The dedicated Vision hardware accelerators provide vision pre-processing

with no impact on system performance. The C7x/MMA cores are available only for deep-learning function in the

AM69 class of processors.

Package Information

PART NUMBER

PACKAGE(1)

PACKAGE SIZE(2)

AM69x

ALY (FCBGA, 1414)

31 mm x 31 mm

XJ784S4

ALY (FCBGA, 1414)

31 mm x 31 mm

(1)

For more information, see the Mechanical, Packaging, and Orderable Information section.

(2)

The package size (length × width) is a nominal value and includes pins, where applicable.

3.1 Functional Block Diagram

Figure 3-1 is functional block diagram for the device.

Note

To understand what device features are currently supported by TI Software Development Kits (SDKs),

see the AM69 Software Build Sheet (PROCESSOR-SDK-AM69) and AM69A Software Build Sheet

(PROCESSOR-SDK-AM69A).

www.ti.com

AM69A, AM69

SPRSP92A – FEBRUARY 2023 – REVISED AUGUST 2023

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