ST7LITE0X datasheet(86/125 Pages) STMICROELECTRONICS

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ST7LITE0x, ST7LITESx

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13.3.4 Internal RC Oscillator and PLL

The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by option byte).

The RC oscillator and PLL characteristics are temperature-dependent and are grouped in two tables.

13.3.4.1 Devices with “6” order code suffix (tested for TA = -40 to +85°C) @ VDD = 4.5 to 5.5V

Notes:

1. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a

decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device.

2. See “INTERNAL RC OSCILLATOR ADJUSTMENT” on page 25

3. Data based on characterization results, not tested in production

4. Averaged over a 4ms period. After the LOCKED bit is set, a period of tSTAB is required to reach ACCPLL accuracy

5. After the LOCKED bit is set ACCPLL is max. 10% until tSTAB has elapsed. See Figure 12 on page 26.

6. Guaranteed by design.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VDD(RC)

Internal RC Oscillator operating voltage

2.4

5.5

VDD(x4PLL)

x4 PLL operating voltage

2.4

3.3

VDD(x8PLL)

x8 PLL operating voltage

3.3

5.5

tSTARTUP

PLL Startup time

PLL input clock (fPLL)

cycles

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fRC

Internal RC oscillator fre-

quency

RCCR = FF (reset value), TA=25°C, VDD=5V

760

kHz

RCCR = RCCR02 ),TA=25°C, VDD=5V

1000

ACCRC

Accuracy of Internal RC

oscillator with

RCCR=RCCR02)

TA=25°C,VDD=4.5 to 5.5V

-1

+1%

TA=-40 to +85°C, VDD=5V

-5

TA=0 to +85°C, VDD=4.5 to 5.5V

-23)

+23)

IDD(RC)

RC oscillator current con-

sumption

TA=25°C,VDD=5V

9703)

µA

tsu(RC)

RC oscillator setup time

TA=25°C,VDD=5V

102)

µs

fPLL

x8 PLL input clock

13)

MHz

tLOCK

PLL Lock time5)

2ms

tSTAB

PLL Stabilization time5)

4ms

ACCPLL

x8 PLL Accuracy

fRC = 1MHz@TA=25°C, VDD=4.5 to 5.5V

0.14)

fRC = 1MHz@TA=-40 to +85°C, VDD=5V

0.14)

tw(JIT)

PLL jitter period

fRC = 1MHz

86)

kHz

JITPLL

PLL jitter (

∆f

CPU/fCPU)1

IDD(PLL)

PLL current consumption TA=25°C

6003)

µA

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