IP101GRI datasheet(16/65 Pages) ETC

16 / 65 page

IP101G

Data Sheet

16/65

January 14, 2014

IP101G-DS-R01

3.2 IP101GR/GRI pin description

IP101GR/GRI

Pin no.

Label

Type

Reset

State

Description

Serial Management Interface Pins

MDC

Hi-Z Management Data Interface Clock: This pin provides a

clock reference to MDIO. The clock period can be to

300ns.

MDIO

I/O

(PU)

Management

Data

interface

Input/Output:

The

function of this pin is to transfer management information

between PHY and MAC.

MII/RMII Pins

TXEN

(PD)

Transmit Enable or Signal Detect.

TXER/FXSD

(PD)

Transmit Error or FXSD:

This is a dual-function pin which is determined by the

media type selection. If RXDV/CRS_DV/FX_HEN is

latched as “0 (default)” upon reset, the TP interface is

selected and its function as TXER. If the fiber interface is

selected, this pin’s function as FXSD.

FXSD:

0: Fiber link down; 1: Fiber link up

Transmit Enable:

TXEN

TXER

Description

Transmission error

propagation.

Combine TXD[3:0] that equal

to 0001 for request PHY to

enter LPI mode.

Normal operation

This pin TXER must be either floating or connecting to

GND in RMII mode.

TXCLK/50M_CLKI

I/O

Hi-Z Transmit Clock output or 50M clock input:

In MII mode, this pin provides a continuous 25MHz clock

at 100Base-TX and 2.5MHz at 10Base-T.

In RMII mode, a 50Mhz clock should input to this pin for

the timing reference of the internal circuit.

6,7,8,9 TXD[3:0]

Hi-Z Transmit Data Input:

In MII mode, TXD[3:0] is synchronous to TXCLK.

In RMII mode, TXD[1:0] is synchronous to 50M_CLKI.

RXDV/CRS_DV/

FX_HEN

O/LI

(PD)

Receive Data Valid or Media Type Selection:

FX_HEN

The input state is latched upon reset to determine

whether TP or fiber interface is selected. If it is at logic

“0” (default) state upon reset, the TP interface is

selected; otherwise the fiber interface is selected.

RXDV/CRS_DV

In MII mode, this pin indicates the Receive Data Valid

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