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STM32L010RB Scheda tecnica(PDF) 53 Page - STMicroelectronics |
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STM32L010RB Scheda tecnica(HTML) 53 Page - STMicroelectronics |
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53 / 89 page ![]() DS12319 Rev 3 53/89 STM32L010RB Electrical characteristics 82 Table 29. Peripheral current consumption in run or Sleep mode(1) Peripheral Typical consumption, VDD = 3.0 V, TA = 25 °C Unit Range 1, VCORE = 1.8 V VOS[1:0] = 01 Range 2, VCORE =1.5 V VOS[1:0] = 10 Range 3, VCORE =1.2 V VOS[1:0] = 11 Low-power sleep and run APB1 WWDG 3 2 2 2 µA/MHz (fHCLK) LPUART1 8 6.5 5.5 6 I2C1 11 9.5 7.5 9 LPTIM1 10 8.5 6.5 8 TIM2 10.5 8.5 7 9 USART2 14.5 12 9.5 11 APB2 ADC1(2) 55 3.5 4 SPI1 4 3 3 2.5 TIM21 7.5 6 5 5.5 DBGMCU 1.5 1 1 0.5 SYSCFG 2.5 2 2 1.5 Cortex-M0+ I/O port GPIOA 3.5 3 2.5 2.5 GPIOB 3.5 2.5 2 2.5 GPIOC 8.5 6.5 5.5 7 GPIOD 1 0.5 0.5 0.5 GPIOH 1.5 1 1 0.5 AHB CRC 1.5 1.1 1 1.2 FLASH(3) 00 0 0 DMA1 10 8 6 8.5 All enabled 121 98 82 92.5 PWR 2.5 2 2 1 1. Data based on differential IDD measurement between all peripherals OFF an one peripheral with clock enabled, in the following conditions: fHCLK = 32 MHz (range 1), fHCLK = 16 MHz (range 2), fHCLK = 4 MHz (range 3), fHCLK = 64 KHz (Low- power run/sleep), fAPB1 = fHCLK, fAPB2 = fHCLK, default prescaler value for each peripheral. The CPU is in Sleep mode in both cases. No I/O pins toggling. Not tested in production. 2. HSI oscillator is OFF for this measure. 3. These values correspond to the Flash memory configuration interface consumption, which is negligible. To assess true Flash memory consumption, compare relevant figures, like for example Table 19 and Table 21. |
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