INS8250 datasheet(2/8 Pages) NSC

2 / 8 page

2 Bit No 6 (TSRE) of the line status register is set as soon

as the transmitter shift register empties whether or not

the transmitter holding register contains a character Bit

No 6 is then reset when the transmitter shift register is

reloaded

Recommendation This will not cause problems in normal

operation However it is a function tested on some popu-

lar 8088-based microcomputer systems diagnostic pro-

grams

3 In loopback mode the modem control outputs RTS DTR

OUT1 and OUT2 remain connected to the associated

Modem Control Register bits

30 INS8250A and NS16450

Function and Timing

Considerations

1 The loopback diagnostic function sets the modem control

outputs RTS DTR OUT1 and OUT2 to their inactive

state (logic ‘‘1’’) so they will send no spurious signals

2 A one byte scratch pad register is included at location

111 This register is not on the INS8250 or -B

3 When multiple interrupts are pending the interrupt line re-

mains high rather than pulsing low after each interrupt is

serviced The INS8250A and NS16450 have level sensi-

tive interrupts as opposed to edge-triggered interrupts

This requires a change in the UART driver software or

associated hardware if the INS8250A NS16450 is used

with some popular microcomputers and their edge-trig-

gered ICUs (see Section 60)

4 Bit 6 of the line status register is set to 1 when both the

transmitter holding and shift register are empty This

causes the INS8250A and NS16450 to be incompatible

with some INS8250 software utilizing this bit

31 TIMING CONSIDERATIONS

1 A start bit will be sent typically 16 clocks (1 bit time) after

the WRTHR signal goes active

2 The leading edge of WRTHR resets THRE and TEMT

3 All of the line status errors and the received data flag

(DR data ready) are set during the time of the first stop

bit

4 TEMT is set 2 RCLK clock periods after the stop bit(s) are

sent

5 The modem control register updates the modem outputs

on the trailing edge of WRMCR

40 INS82C50A and NS16C450

Function and Timing

Considerations

All of the information presented in Sections 30 through 32

is applicable to the CMOS parts In addition the following

items specify differences between XMOS and CMOS parts

They are applicable to the CMOS parts only

1 Anytime a reset pulse is issued to the INS82C50A or

NS16C450 the divisor latches must be rewritten with the

appropriate divisors in order to start the baud rate gener-

ator

2 tSI is from 16 to 48 RCLK cycles in length

50 NS16550AF and NS16550 Func-

tion and Timing Considerations

All of the information present in Sections 30 and 31 is ap-

plicable to the NS16550AF and NS16550

The primary difference between these two parts is in the

operation of the FIFOs The NS16550 will sometimes trans-

fer extra characters when the CPU reads the RX FIFO Due

to the asynchronous nature of this failure there is no work-

around and the NS16550 should NOT be used in the FIFO

mode The NS16550AF has no problems operating in the

FIFO mode and should be used on all new designs

The programmer should note the difference in the function

of bit 6 in the Interrupt Identification Register (IIR6) This bit

is permanently at logical 0 in the NS16550

In the

NS16550AF this bit will be set to a 1 when the FIFOs are

enabled In both parts bit 7 of the IIR is set to a 1 when the

FIFOs are enabled Therefore the program can distinguish

when the FIFOs are enabled and whether the part is an

NS16550AF or an NS16550 by checking these two bits In

order to enable the FIFO mode and set IIR6 and IIR7 bit 0 of

the FIFO Control Register (FCR0) should be set Remember

unless both bits IIR6 and IIR7 are set the program should

not transfer data via the FIFOs

The following are improvements in the AC timings for the

NS16550AF over the NS16450

1 tAR changes from 60 ns to 30 ns

2 tCSW changes from 50 ns to 30 ns

3 tCSR changes from 50 ns to 30 ns

4 RC changes from 360 ns to 280 ns

5 tRC changes from 175 ns to 125 ns

6 tDS changes from 40 ns to 30 ns

7 tDH changes from 40 ns to 30 ns

8 tAW changes from 60 ns to 30 ns

9 tWC changes from 200 ns to 150 ns

10 WC changes from 360 ns to 280 ns

11 Timing parameters specified by tSINT will change in

some cases when the FIFOs are enabled Refer to the

data sheet for specific changes

TLC9320 – 2

FIGURE 2 Serial Data Timing

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