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AD9549 Scheda tecnica(PDF) 57 Page - Analog Devices

Il numero della parte AD9549
Spiegazioni elettronici  Dual Input Network Clock Generator/Synchronizer
PDF  78 Pages
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD9549 Scheda tecnica(HTML) 57 Page - Analog Devices

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Preliminary Technical Data
AD9549
Rev. PrA | Page 57 of 78
tDS
Setup time between data and rising edge of SCLK
tDH
Hold time between data and rising edge of SCLK
tCLK
Period of the clock
tS
Setup time between CSB and SCLK
tH
Hold time between CSB and SCLK
tHI
Minimum period that SCLK should be in a logic high state
tLO
Minimum period that SCLK should be in a logic low state
Table 8: Definitions of Terms Used Serial Control Port Timing Diagrams



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