5CEBA2F15C6SC datasheet(37/37 Pages) INTEL

37 / 37 page

Date

Version

Changes

• Updated Figure 1, Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, and

Figure 10.

• Updated the “FPGA Configuration and Processor Booting” and “Hardware

and Software Development” sections.

• Text edits throughout the document.

February 2012

1.2

• Updated Table 1–2, Table 1–3, and Table 1–6.

• Updated “Cyclone V Family Plan” on page 1–4 and “Clock Networks and

PLL Clock Sources” on page 1–15.

• Updated Figure 1–1 and Figure 1–6.

November 2011

1.1

• Updated Table 1–1, Table 1–2, Table 1–3, Table 1–4, Table 1–5, and Table

1–6.

• Updated Figure 1–4, Figure 1–5, Figure 1–6, Figure 1–7, and Figure 1–8.

• Updated “System Peripherals” on page 1–18, “HPS–FPGA AXI Bridges” on

page 1–19, “HPS SDRAM Controller Subsystem” on page 1–19, “FPGA

Configuration and Processor Booting” on page 1–19, and “Hardware and

Software Development” on page 1–20.

• Minor text edits.

October 2011

1.0

Initial release.

Cyclone V Device Overview

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Cyclone V Device Overview

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