WM8196

Production Data

w

PD Rev 4.3 March 2007

16

ADC INPUT BLACK LEVEL ADJUST

The output from the PGA should be offset to match the full-scale range of the ADC (3V). For

negative-going input video signals, a black level (zero differential) output from the PGA should be

offset to the top of the ADC range by setting register bits PGAFS[1:0]=10. For positive going input

signal the black level should be offset to the bottom of the ADC range by setting PGAFS[1:0]=11.

Bipolar input video is accommodated by setting PGAFS[1:0]=00 or PGAFS[1:0]=01 (zero differential

input voltage gives mid-range ADC output).

OVERALL SIGNAL FLOW SUMMARY

Figure 14 represents the processing of the video signal through the WM8196.

V

RESET

V

VRLC

V

3

CDS = 1

CDS = 0

RLCEXT=1

260mV*(DAC[7:0]-127.5)/127.5

analog

-

X

+

+

See parametrics for

DAC voltages.

OP[7:0]

D

1

digital

ADC BLOCK

PGA

BLOCK

OFFSET DAC

BLOCK

INPUT

SAMPLING

BLOCK

D

2

CDS, RLCEXT,RLCV[3:0], DAC[7:0],

PGA[7:0], PGAFS[1:0] and INVOP are set

by programming internal control registers.

CDS=1 for CDS, 0 for non-CDS

V

V

VRLC is voltage applied to VRLC pin

V

IN

x (65535/V

+0

if PGAFS[1:0]=11

+65535 if PGAFS[1:0]=10

+32768 if PGAFS[1:0]=0x

PGA gain

A = 208/(283-PGA[7:0])

OUTPUT

INVERT

BLOCK

D2 = D1 if INVOP = 0

D2 = 65535-D1 if INVOP = 1

Offset

DAC

RLC

DAC

+

V

2

V

1

RLCEXT=0

Figure 14 Overall Signal Flow

optionally set via the RLC DAC.

The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the

The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range,

CALCULATING OUTPUT FOR ANY GIVEN INPUT

The following equations describe the processing of the video and reset level signals through

setup. The PGA value is written first to set the input Voltage range, the Offset DAC is then

adjusted to compensate for any Black/Reset level offsets and finally the RLC DAC value is

set to position the reset level correctly during operation.

Note: Refer to WAN0123 for detailed information on device calibration procedures.

INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING

input video.

=

Eqn. 1

If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted

instead.

=

Eqn. 2