WM8199

Production Data

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PD Rev 4.3 March 2007

7

Test Conditions

°C, MCLK = 32MHz unless otherwise stated.

PARAMETER

SYMBOL

TEST

CONDITIONS

MIN

TYP

MAX

UNIT

Programmable Gain Amplifier

Resolution

8

bits

Gain

]

0

:

7

[

PGA

283

208

−

V/V

Max gain, each channel

7.43

V/V

Min gain, each channel

0.74

V/V

Gain error, each channel

1

%

Analogue to Digital Converter

Resolution

16

bits

Speed

16

MSPS

Full-scale input range

(2*(VRT-VRB))

3

V

DIGITAL SPECIFICATIONS

Digital Inputs

High level input voltage

0.8

∗ DVDD2

V

Low level input voltage

0.2

∗ DVDD2

V

High level input current

1

µA

Low level input current

1

µA

Input capacitance

5

pF

Digital Outputs

High level output voltage

DVDD2 - 0.5

V

Low level output voltage

0.5

V

High impedance output current

1

µA

Digital IO Pins

Applied high level input voltage

0.8

∗ DVDD2

V

Applied low level input voltage

0.2

∗ DVDD2

V

High level output voltage

DVDD2 - 0.5

V

Low level output voltage

0.5

V

Low level input current

1

µA

High level input current

1

µA

Input capacitance

5

pF

High impedance output current

1

µA

Supply Currents

Total supply current

− active

(Three channel mode)

MCLK = 32Hz

72

mA

Total supply current

− active

(Single channel mode)

LINEBYLINE = 1

MCLK = 32MHz

56

mA

Total analogue supply current

−

active (Three channel mode)

MCLK = 32MHz

65

mA

Total analogue supply current

−

active (Single channel mode)

LINEBYLINE = 1

MCLK = 32MHz

49

mA

Digital core supply current,

DVDD1

− active (note 1)

MCLK = 32MHz

5

mA

Digital I/O supply current,

DVDD2

− active (note 1)

MCLK = 32MHz

2

mA

Supply current

− full power down

mode

300

µA

Notes:

Digital supply current depends on the capacitive load connected to the WM8199 output pins and the clock rate applied to

MCLK. This data is based on a load of approximately 10pF per output pin and MCLK = 16MHz.