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enabled. The fault threshold is 150 mV (typical) below the input voltage level for boost. Boost converter is

disabled if the output voltage is below the threshold level 1 ms after the boost converter is enabled.

In a similar way, the overload situation is protected during normal operation. If the feedback-pin voltage of the

buck converter falls below 0.35 V and remains below the threshold level for 1 ms, the buck converter is disabled.

If the output voltage of the boost converter decreases 150 mV below the input voltage level, the converter is

disabled after 1 ms. If the output voltage decreases to 2.5 V, the boost is disabled immediately.

The BUCKx_SC_INT and the BUCK_INT bits are set to 1, the BUCKx_STAT bit is set to 0, and the nINT

signal is pulled low in the buck converter, the short-circuit, and overload situations. The BOOST_SC_INT and

the BOOST_INT bits are set to 1, the BOOST_STAT bit is set to 0, and the nINT signal is pulled low in the

boost converter, short-circuit, and overload situations. The host processor clears the interrupt by writing 1 to

the BUCKx_SC_INT or BOOST_SC_INT bit. The converter makes a new start-up attempt upon clearing the

interrupt, if the converter is in the enabled state.

8.3.10.5.2 Overvoltage Protection

The LP87702-Q1 device monitors the input voltage from the VANA pin in the standby and active operation

modes. If the input voltage rises above the VANAOVP voltage level, all the converters are disabled

immediately (without switching ramp or shutdown delays), the pulldown resistors discharge the output voltages

(BUCKx_RDIS_EN = 1 and BOOST_RDIS_EN = 1), the GPOs are set to the logic low level, the nINT signal

is pulled low, the OVP_INT bit is set to 1, and BUCKx_STAT and BOOST_STAT bits are set to 0. The host

processor clears the interrupt by writing 1 to the OVP_INT bit. If the input voltage is above over-voltage

detection level, the interrupt is not cleared. The host can read the status of the overvoltage from the OVP_STAT

bit. Converters cannot be enabled as long as the input voltage is above over-voltage detection level or the

overvoltage interrupt is pending.

8.3.10.5.3 Thermal Shutdown

The LP87702-Q1 has an overtemperature protection function that operates to protect itself from short-term

misuse and overload conditions. The converters are disabled immediately (without switching ramp or shutdown

delays), the TDIE_SD_INT bit is set to 1, the nINT signal is pulled low, and the device enters STANDBY when

the junction temperature exceeds around 150°C. The nINT is cleared by writing 1 to the TDIE_SD_INT bit. If

the temperature is above thermal shutdown level, the interrupt is not cleared. The host can read the status

of the thermal shutdown from the TDIE_SD_STAT bit. Converters cannot be enabled as long as the junction

temperature is above the thermal shutdown level or the thermal shutdown interrupt is pending.

8.3.10.6 Protections Causing Device Power Down

8.3.10.6.1 Undervoltage Lockout

The buck and boost converters are disabled immediately (without switching ramp or without any shutdown

delays), and the output capacitor is discharged using the pulldown resistor, and the LP87702-Q1 device enters

SHUTDOWN when the input voltage falls below VANAUVLO at the VANA pin. The device powers up to STANDBY

state when the V(VANA) voltage is above the VANAUVLO threshold level.

If the reset interrupt is unmasked by default (RESET_REG_MASK = 0 in TOP_MASK_2 register), the

RESET_REG_INT interrupt in the INT_TOP_2 register indicates that the device has been in SHUTDOWN. The

host processor must clear the interrupt by writing 1 to the RESET_REG_INT bit. If the host processor reads the

RESET_REG_INT flag after detecting an nINT low signal, it detects that the input supply voltage has been below

the VANAUVLO level (or the host has requested reset with the RESET(SW_RESET) bit), and the registers are

reset to the default values.

8.3.11 OTP Error Correction

LP87702-Q1 supports the OTP bit error detection and 1-bit error correction per five registers. The ECC_STATUS

been detected in any bank of five registers.

8.3.12 Operation of GPO Signals

The LP87702-Q1 device supports up to 3 general purpose output (GPO) signals. The GPO1 signal is

multiplexed with the PG1 signal and GPO2 signal is multiplexed with the CLKIN and WD_DIS signals. The

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LP87702-Q1

SNVSAL1C – DECEMBER 2017 – REVISED JUNE 2021

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