DS26519G+ datasheet(2/310 Pages) MAXIM

2 / 310 page

DS26519 16-Port T1/E1/J1 Transceiver

2 of 310

TABLE OF CONTENTS

DETAILED DESCRIPTION.................................................................................................9

FEATURE HIGHLIGHTS ..................................................................................................10

2.1

GENERAL ......................................................................................................................................10

2.2

LINE INTERFACE ............................................................................................................................10

2.3

CLOCK SYNTHESIZERS ..................................................................................................................10

2.4

JITTER ATTENUATOR .....................................................................................................................10

2.5

FRAMER/FORMATTER ....................................................................................................................11

2.6

SYSTEM INTERFACE ......................................................................................................................11

2.7

HDCL CONTROLLERS ...................................................................................................................12

2.8

TEST AND DIAGNOSTICS ................................................................................................................12

2.9

MICROCONTROLLER PARALLEL PORT.............................................................................................12

2.10

SLAVE SERIAL PERIPHERAL INTERFACE (SPI) FEATURES ............................................................12

APPLICATIONS ...............................................................................................................13

SPECIFICATIONS COMPLIANCE ...................................................................................14

ACRONYMS AND GLOSSARY .......................................................................................16

MAJOR OPERATING MODES.........................................................................................17

BLOCK DIAGRAMS.........................................................................................................18

PIN DESCRIPTIONS ........................................................................................................20

8.1

PIN FUNCTIONAL DESCRIPTION......................................................................................................20

FUNCTIONAL DESCRIPTION .........................................................................................33

9.1

PROCESSOR INTERFACE................................................................................................................33

9.1.1

SPI Serial Port Mode............................................................................................................................ 33

9.1.2

SPI Functional Timing Diagrams ......................................................................................................... 33

9.2

CLOCK STRUCTURE.......................................................................................................................35

9.2.1

Backplane Clock Generation ............................................................................................................... 35

9.2.2

CLKO Output Clock Generation........................................................................................................... 37

9.3

RESETS AND POWER-DOWN MODES..............................................................................................38

9.4

INITIALIZATION AND CONFIGURATION..............................................................................................39

9.4.1

Example Device Initialization and Sequence ....................................................................................... 39

9.5

GLOBAL RESOURCES ....................................................................................................................40

9.5.1

General-Purpose I/O Pins .................................................................................................................... 40

9.6

PER-PORT RESOURCES ................................................................................................................40

9.7

DEVICE INTERRUPTS .....................................................................................................................41

9.8

SYSTEM BACKPLANE INTERFACE ...................................................................................................43

9.8.1

Elastic Stores ....................................................................................................................................... 43

9.8.2

IBO Multiplexing ................................................................................................................................... 46

9.8.3

H.100 (CT Bus) Compatibility .............................................................................................................. 55

9.8.4

Transmit and Receive Channel Blocking Registers............................................................................. 57

9.8.5

Transmit Fractional Support (Gapped Clock Mode) ............................................................................ 57

9.8.6

Receive Fractional Support (Gapped Clock Mode) ............................................................................. 57

9.9

FRAMERS......................................................................................................................................58

9.9.1

T1 Framing........................................................................................................................................... 58

9.9.2

E1 Framing........................................................................................................................................... 61

9.9.3

T1 Transmit Synchronizer .................................................................................................................... 63

9.9.4

Signaling .............................................................................................................................................. 64

9.9.5

T1 Data Link......................................................................................................................................... 69

9.9.6

E1 Data Link......................................................................................................................................... 71

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