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AT89LP4052 Scheda tecnica(PDF) 71 Page - ATMEL Corporation |
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AT89LP4052 Scheda tecnica(HTML) 71 Page - ATMEL Corporation |
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71 / 90 page ![]() 71 3547F–MICRO–6/06 AT89LP2052/LP4052 Figure 22-21. ISP/Serial Programming Device Connections Note: SCK frequency should be less than 5 MHz. 22.5.1 Power-up Sequence Execute this sequence to power-up the device before serial programming. 1. Apply power between VCC and GND pins. 2. Keep SCK (P1.7) and SS (P1.4) at “L”. 3. Wait 10 µs and bring RST and SS to “H”. 4. Wait at least 2 ms for internal Power-on Reset to time out. Figure 22-22. Serial Programming Power-up Sequence AT89LP2052/LP4052 VCC RST P1.7/SCK P1.5/MOSI GND 2.7 to 5.5V Serial Clock Se rial In VIH P1.4/SS P1.6/MISO Serial Out CS VCC RST SS SCK HIGH Z MISO HIGH Z MOSI |
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