AT83SND1CXXX-ROTUL datasheet(57/212 Pages) ATMEL

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4109J–8051–10/06

AT8xC51SND1C

Reset Value = 0000 0000b

Bit

Number

Bit

Mnemonic

Description

TF1

Timer 1 Overflow Flag

Cleared by hardware when processor vectors to interrupt routine.

Set by hardware on Timer/Counter overflow, when Timer 1 register overflows.

6TR1

Timer 1 Run Control Bit

Clear to turn off Timer/Counter 1.

Set to turn on Timer/Counter 1.

TF0

Timer 0 Overflow Flag

Cleared by hardware when processor vectors to interrupt routine.

Set by hardware on Timer/Counter overflow, when Timer 0 register overflows.

4TR0

Timer 0 Run Control Bit

Clear to turn off Timer/Counter 0.

Set to turn on Timer/Counter 0.

3IE1

Interrupt 1 Edge Flag

Cleared by hardware when interrupt is processed if edge-triggered (see IT1).

Set by hardware when external interrupt is detected on INT1 pin.

2IT1

Interrupt 1 Type Control Bit

Clear to select low level active (level triggered) for external interrupt 1 (INT1).

Set to select falling edge active (edge triggered) for external interrupt 1.

1IE0

Interrupt 0 Edge Flag

Cleared by hardware when interrupt is processed if edge-triggered (see IT0).

Set by hardware when external interrupt is detected on INT0 pin.

0IT0

Interrupt 0 Type Control Bit

Clear to select low level active (level triggered) for external interrupt 0 (INT0).

Set to select falling edge active (edge triggered) for external interrupt 0.

Table 51. TMOD Register

TMOD (S:89h) – Timer/Counter Mode Control Register

7654

3210

GATE1

C/T1#

M11

M01

GATE0

C/T0#

M10

M00

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