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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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AT80C51RB2-3CSIM Scheda tecnica(PDF) 10 Page - ATMEL Corporation |
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AT80C51RB2-3CSIM Scheda tecnica(HTML) 10 Page - ATMEL Corporation |
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10 / 83 page  11 AT80C51RD2/AT83C51Rx2 4113B–8051–03/05 Figure 3. Mode Switching Waveforms The X2 bit in the CKCON0 register (see Table 5) allows to switch from 12 clock periods per instruction to 6 clock periods and vice versa. At reset, the speed is set according to X2 bit of Hardware Config Byte (HCB). By default, Standard mode is activated. Setting the X2 bit activates the X2 feature (X2 mode). The T0X2, T1X2, T2X2, UARTX2, PCAX2 and WDX2 bits in the CKCON0 register (Table 5) allow to switch from standard peripheral speed (12 clock periods per periph- eral clock cycle) to fast peripheral speed (6 clock periods per peripheral clock cycle). These bits are active only in X2 mode. XTAL1:2 CPU Block X2 Bit X2 Mode STD Mode STD Mode FOSC XTAL1 |
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