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3940 Scheda tecnica(PDF) 8 Page - Allegro MicroSystems |
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3940 Scheda tecnica(HTML) 8 Page - Allegro MicroSystems |
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8 / 12 page ![]() 3940 FULL-BRIDGE POWER MOSFET CONTROLLER 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 8 Terminal Descriptions CA/CB. High-side connection for bootstrap capacitor, positive supply for high-side gate drive. The bootstrap capacitor is charged to V REG13 – 1.5 V when the output Sx terminal is low. When the output swings high, the voltage on this terminal rises with the output to provide the boosted gate voltage needed for n- channel power MOSFETs. RESET. Control input to put device into minimum power consumption mode and to clear latched faults. Logic “1” enables the device; logic “0” triggers the sleep mode. Internally pulled down via 50 k Ω resistor. ENABLE. Logic “1” enables direct control of the output drivers via the PHASE input, as in PWM controls, and ignores the MODE and SR inputs. Internally pulled down via 50 k Ω resistor. MODE. Logic input to set the current decay mode. Logic “1” (slow-decay mode) switches off the high-side MOSFET in response to a PWM “off” command. Logic “0” (fast-decay mode) switches off both the high-side and low-side MOSFETs. Internally pulled down via 50 k Ω resistor. PHASE. Motor direction control. When logic “1”, enables gate drive outputs GHA and GLB allowing current flow from SA to SB. When logic “0”, enables GHB and GLA allowing current flow from SB to SA. Internally pulled down via 50 k Ω resistor. SR. When logic “1”, enables synchronous rectification; logic “0” disables the synchronous rectification. Internally pulled down via 50 k Ω resistor. FAULT. Open drain, diagnostic logic output signal. When logic “1”, indicates that one or more fault conditions have occurred. Use an external pullup resistor to VREG5 or to digital controller. Internally causes a coast when asserted. See also Functional Description, next page. IDEAD. Analog current set by resistor (12 k Ω<R DEAD<500 kΩ) to ground. In conjunction with LONG, determines dead time between GHx and GLx transitions of same phase. VIDEAD = 2 V. LONG. When logic “1”, selects long dead time between GHx and GLx transitions of same phase. When logic “0”, selects short dead times. Internally pulled down via 50 k Ω resistor. GHA/GHB. High-side gate-drive outputs for n-channel MOSFET drivers. External series gate resistors can control slew rate seen at the power driver gate. GLA/GLB. Low-side gate drive outputs for external, n-channel MOSFET drivers. External series gate resistors can control slew rate seen at the power driver gate. GND. Common ground and dc supply returns. Exposed thermal pad of LP package is NOT internally connected to GND. LSS. Low-side gate drivers’ return. Connects to the common sources in the low-side of the power MOSFET bridge. It is the reference connection for the short-to-battery monitor. OVSET. A positive, dc level that controls the VBB overvoltage trip point. Usually, provided from precision resistor divider network between V REG5 and GND. If connected directly to V REG5, sets unspecified but high overvoltage trip point, effec- tively eliminating the overvoltage protection. SA/SB. Directly connected to the motor terminals, these terminals sense the voltages switched across the load and are connected to the negative side of the bootstrap capacitors. Also, are the negative supply connection for the floating, high-side drivers. VBB. Positive supply voltage. Usually connected to the motor voltage supply. If VBB is above a specified level or below a specified level, a fault will be asserted. VDRAIN. Kelvin connection for drain-to-source voltage (short- to-ground) monitor and is connected to high-side drains of the MOSFET bridge. Also used to detect “open drain”. VDSTH. A positive, dc level that sets the short-to-ground and short-to-battery monitor threshold voltage. If the drain-source voltage exceeds this level (after the dead time) during an “on” state, a fault will be asserted. CP1 [CP2]. Charge pump capacitor negative [positive] side. If not using the charge pump, leave both terminals open. VCP. Charge pump output for VREG13 input. If not using the charge pump, connect this terminal to VBB. VIN. Positive supply voltage for the V REG13 linear regulator. Usually connected to VCP, the charge-pump output gate drive. If not using the charge pump, connect VIN to VBB or other dc supply greater than 11 V. VREG13. High-side, gate-driver supply. If V REG13 falls below a specified level, a fault will be asserted. VREG5. Regulated 5 V output for internal logic. |
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