56F803 datasheet(49/57 Pages) FREESCALE

49 / 57 page

56F803 Technical Data, Rev. 16

Freescale Semiconductor

Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)

Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)

Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)

Sampling capacitor at the sample and hold circuit. (1pf)

Figure 3-26 Equivalent Analog Input Circuit

3.13 Controller Area Network (CAN) Timing

ADC Quiescent Current (both ADCs)

IADC

—50

—

VREF Quiescent Current (both ADCs)

IVREF

—12

16.5

For optimum ADC performance, keep the minimum VADCIN value > 25mV. Inputs less than 25mV may convert to a digital

output code of 0.

VREF must be equal to or less than VDDA and must be greater than 2.7V. For optimal ADC performance, set VREF to VD-

DA-0.3V.

Measured in 10-90% range.

LSB = Least Significant Bit.

Guaranteed by characterization.

tAIC = 1/fADIC

Table 3-17 CAN Timing2

Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40× to +85×C, CL £ 50pF, MSCAN Clock = 30MHz

Characteristic

Symbol

Min

Max

Unit

Baud Rate

BRCAN

—1

Mbps

Bus Wakeup detection 1

T WAKEUP

5—

μs

Table 3-16 ADC Characteristics

Characteristic

Symbol

Min

Typ

Max

Unit

ADC analog input

56F803 Scheda tecnica(PDF) 49 Page - Freescale Semiconductor, Inc

56F803 Scheda tecnica(HTML) 49 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

Scheda tecnica Scarica

Link URL