6.7 Electrical Characteristics

For VS = (V+) – (V–) = 2.7 V to 40 V (±1.35 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and

VO UT = VS / 2, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OFFSET VOLTAGE

VOS

Input offset voltage

VCM = V–

±0.3

±1.5

mV

TA = –40°C to 125°C

±1.75

dVOS/dT

Input offset voltage drift

TA = –40°C to 125°C

±0.6

µV/

℃

PSRR

Input offset voltage versus

power supply

VCM = V–, VS = 4 V to 40 V

TA = –40°C to 125°C

±0.1

±1.3

µV/V

VCM = V–, VS = 2.7 V to 40 V(1)

±0.75

±6.6

Channel separation

f = 0 Hz

5

µV/V

INPUT BIAS CURRENT

IB

Input bias current

±10

pA

IOS

Input offset current

±5

pA

NOISE

EN

Input voltage noise

f = 0.1 Hz to 10 Hz

6

µVPP

1

µVRMS

eN

Input voltage noise density

f = 1 kHz

30

nV/√Hz

f = 10 kHz

28

iN

Input current noise

f = 1 kHz

2

fA/√Hz

INPUT VOLTAGE RANGE

VCM

Common-mode voltage

range

(V–) – 0.2

(V+) + 0.2

V

CMRR

Common-mode rejection

ratio

VS = 40 V, (V–) – 0.1 V < VCM <

(V+) – 2 V (PMOS pair)

TA = –40°C to 125°C

100

115

dB

VS = 4 V, (V–) – 0.1 V < VCM <

(V+) – 2 V (PMOS pair)

75

90

VS = 2.7 V, (V–) – 0.1 V < VCM <

(V+) – 2 V (PMOS pair)(1)

70

90

VS = 2.7 – 40 V, (V+) – 1 V < VCM

< (V+) + 0.1 V (NMOS pair)

80

(V+) – 2 V < VCM < (V+) – 1 V

For more information, see Offset Voltage (Transition

Region) in the Typical Characteristics section

INPUT CAPACITANCE

ZID

Differential

540 || 3

GΩ || pF

ZICM

Common-mode

6 || 1

TΩ || pF

OPA4990-Q1

SBOSAH7 – OCTOBER 2023

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