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AM263P4 Scheda tecnica(PDF) 63 Page - Texas Instruments |
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AM263P4 Scheda tecnica(HTML) 63 Page - Texas Instruments |
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63 / 154 page  Table 5-96. PRU-ICSS UART Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ZCZ C PIN [4] ZCZ S PIN [4] PR0_UART0_CTSn I PRU-ICSS UART Clear to Send (Active Low) F17 F17 PR0_UART0_RTSn O PRU-ICSS UART Request to Send (Active Low) G18 G18 PR0_UART0_RXD I PRU-ICSS UART Receive Data C18 C18 PR0_UART0_TXD O PRU-ICSS UART Transmit Data D17 D17 5.3.19 OSPI Table 5-97. OSPI0 Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ZCZ C PIN [4] ZCZ S PIN [4] OSPI0_CLK O OSPI Clock L2, N2 L2, N2 OSPI0_CLKLB (4) IO OSPI Clock Loopback LB LB OSPI0_DQS I OSPI Data Strobe (DQS) or Loopback Clock input M1, M3 M1, M3 OSPI0_ECC_FAIL I OSPI ECC Failure Status Pin A9, H1, K3 A9, H1, K3 OSPI0_LBCLKO (3) O OSPI Loopback Clock output L3 L3 OSPI0_CSn0 O OSPI Chip Select 0 H1, P1 H1, P1 OSPI0_CSn1 O OSPI Chip Select 1 R3 R3 OSPI0_D0 (1) IO OSPI Data bit 0 (SOP0) N1, P1 N1, P1 OSPI0_D1 (2) IO OSPI Data bit 1 (SOP1) J1, N4 J1, N4 OSPI0_D2 IO OSPI Data bit 2 L1, M4 L1, M4 OSPI0_D3 IO OSPI Data bit 3 K4, P3 K4, P3 OSPI0_D4 IO OSPI Data bit 4 M1, P3 M1, P3 OSPI0_D5 IO OSPI Data bit 5 K2, L1 K2, L1 OSPI0_D6 IO OSPI Data bit 6 L2, M4 L2, M4 OSPI0_D7 IO OSPI Data bit 7 J4, K1 J4, K1 OSPI0_RESET_OUT0 O OSPI Reset Out 0 B9, J1, J3 B9, J1, J3 OSPI0_RESET_OUT1 O OSPI Reset Out 1 A9, H1 A9, H1 (1) The OSPI0_D0 pin is also used as SOP0 boot mode configuration pin. (2) The OSPI0_D1 pin is also used as SOP1 boot mode configuration pin. (3) OSPI0_LBCLKO is a clock loopback output signal used for peripheral timing. (4) OSPI0_CLKLB is a clock loopback signal used internally for retiming purposes. 5.3.20 SDFM Table 5-98. SDFM0 Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ZCZ C PIN [4] ZCZ S PIN [4] SDFM0_CLK0 I SDFM Channel 0 Clock B16 B16 SDFM0_CLK1 I SDFM Channel 1 Clock A16 A16 SDFM0_CLK2 I SDFM Channel 2 Clock B15 B15 SDFM0_CLK3 I SDFM Channel 3 Clock A15 A15 SDFM0_D0 I SDFM Channel 0 Data D14 D14 SDFM0_D1 I SDFM Channel 1 Data D13 D13 SDFM0_D2 I SDFM Channel 2 Data C13 C13 SDFM0_D3 I SDFM Channel 3 Data C14 C14 Table 5-99. SDFM1 Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ZCZ C PIN [4] ZCZ S PIN [4] SDFM1_CLK0 I SDFM Channel 0 Clock B14, B6 B14, B6 SDFM1_CLK1 I SDFM Channel 1 Clock B5, C12 B5, C12 SDFM1_CLK2 (1) I SDFM Channel 2 Clock A3, B13 A3, B13 SDFM1_CLK3 (2) IOD SDFM Channel 3 Clock A13, C6 A13, C6 SDFM1_D0 I SDFM Channel 0 Data A14, A4 A14, A4 SDFM1_D1 I SDFM Channel 1 Data B4, D11 B4, D11 TI Information - Selective Disclosure www.ti.com AM263P4, AM263P2, AM263P1, AM263P4-Q1, AM263P2-Q1, AM263P1-Q1 SPRSP81 – OCTOBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 63 |
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