SC1933C datasheet(16/28 Pages) POWERINT

16 / 28 page

Rev. C 11/18

SC1933C/SC1936C

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Typical margin (150 V)

gives de-rating of >80%

Safe Surge Voltage

Region (SSVR)

VCLM

750 V = VMAX(NON-REPETITIVE)

650 V = VMAX(CONTINUOUS)

Primary Switch Voltage Stress (264 VAC)

380 VDC

VOR

VBUS

PI-8769-071218

Figure 15. Peak Drain Voltage for 264 VAC Input Voltage.

Switching Frequency (f

SW)

It is a unique feature in SC1933C/SC1936C that for full load, the

designer can set the switching frequency to between 25 kHz to 95

kHz. For lowest temperature, the switching frequency should be set

to around 60 kHz. For a smaller transformer, the full load switching

frequency needs to be set to 95 kHz. When setting the full load

switching frequency it is important to consider primary inductance

and peak current tolerances to ensure that average switching

frequency does not exceed 110 kHz which may trigger auto-restart

due to overload protection. The following table provides a guide to

frequency selection based on device size. This represents the best

compromise between overall device losses (conduction losses and

switching losses) based on the size of the integrated high-voltage

switch.

SC1933C

65 kHz

SC1936C

60 kHz

Drain Voltage and Reflected Output Voltage, V

OR (V)

For a flyback converter configuration, typical voltage waveform at the

DRAIN pin of the IC is shown in Figure 15.

OR is the reflected output voltage across the primary winding when

the secondary is conducting. V

BUS is the DC voltage connected to one

end of the transformer primary winding.

In addition to V

BUS+VOR, the drain also sees a large voltage spike at

turn off that is caused by the energy stored in the leakage inductance

of the primary winding. To keep the drain voltage from exceeding the

rated maximum continuous drain voltage, a clamp circuit is needed

across the primary winding. The forward recovery of the clamp diode

will add a spike at the instant of turn-OFF of the primary switch. V

CLM

in Figure 15 is the combined clamp voltage including the spike. The

peak drain voltage of the primary switch is the total of V

BUS, VOR and

CLM.

OR and the clamp voltage VCLM should be selected such that the

peak drain voltage is lower than 650 V for all normal operating

conditions. This provides sufficient margin to ensure that occasional

increase in voltage during line transients such as line surges will

maintain the peak drain voltage well below 750 V under abnormal

transient operating conditions. This ensures excellent long term

reliability and design margin.

To make full use of QR capability and ensure flattest efficiency over

line/load, set reflected output voltage (VOR) to maintain K

P = 0.8 at

minimum input voltage for universal input and K

P ≥ 1 for high-line-

only conditions.

Consider the following for design optimization:

1. Higher V

OR allows increased power delivery at VMIN, which

minimizes the value of the input capacitor and maximizes power

delivery from a given SC1933C/SC1936C device.

2. Higher V

OR reduces the voltage stress on the output diodes and

SR FETs.

3. Higher V

OR increases leakage inductance which reduces power

supply efficiency.

4. Higher V

OR increases peak and RMS current on the secondary-side

which may increase secondary-side copper and diode losses.

There are some exceptions to this. For very high output currents the

VOR should be reduced to get highest efficiency. For output voltages

above 15 V, VOR should be maintained higher to maintain an

acceptable PIV across the output synchronous rectifier.

OR choice will affect the operating efficiency and should be selected

carefully. Table below shows the typical range of V

OR for optimal

performance:

Output Voltage

Optimal Range for VOR

5 V

45 - 70

12 V

80 - 120

15 V

100 - 135

20 V

120 - 150

24 V

135 - 180

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