ES9018 datasheet(12/35 Pages) ESS

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Sabre32 Reference Datasheet

CONFIDENTIAL ADVANCE

INFORMATION Rev. 1.2

February 11, 2010

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Sample Rate Calculation

The DPLL number can be read back from the SABRE

32 Reference, allowing for calculation of the sample

rate. The sample rate can be calculated using: Fin = (DPLL_NUM * Fcrystal) / 2

32 . F

in must be divided by

64 for I

2S data.

DAC-bar Phase

Each DAC-bar phase can be configured to be in phase with DAC. This allows for the outputs of the DAC

to be summed to drive an amplifier.

DPLL Lock Reset

The DPLL can be forced to relock, which is useful when the sample rate has been changed. This can be

done by setting Register 17 <dpll_lock_rst_reg> high to force the reset, and then low to resume normal

operation.

DPLL Frequency Phase Flip

The DPLL can be set to lock to either the rising or falling edge of the clock. This can be set using

PCM Audio Interface Formats

Several interface formats are provided so that direct connection to common audio processors is possible.

The available formats and their accompanying diagrams are listed in the following table. The audio

interface format can be set by programming the registers.

Format

Description

Figure

MSB First, Left Justified, up to 32-bit data

I2S, up to 32-bit data

MSB First, Right Justified, 32-bit data

MSB First, Right Justified, 24-bit data

MSB First, Right Justified, 20-bit data

MSB First, Right Justified, 16-bit data

DSD Normal Mode

DSD Phase Mode

Table 6

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