TMS320F datasheet(32/389 Pages) TI

32 / 389 page

Central Processing Unit

2-9

Architectural Overview

2.4.3

Multiplier

The on-chip multiplier performs 16-bit

× 16-bit 2s-complement multiplication

with a 32-bit result. In conjunction with the multiplier, the ’C24x uses the 16-bit

temporary register (TREG) and the 32-bit product register (PREG); TREG al-

ways supplies one of the values to be multiplied, and PREG receives the result

of each multiplication.

Using the multiplier, TREG, and PREG, the ’C24x efficiently performs funda-

mental DSP operations such as convolution, correlation, and filtering. The ef-

fective execution time of each multiplication instruction can be as short as one

CPU cycle.

2.4.4

Auxiliary Register Arithmetic Unit (ARAU) and Auxiliary Registers

The ARAU generates data memory addresses when an instruction uses indi-

rect addressing (see Chapter 6,

Addressing Modes) to access data memory.

The ARAU is supported by eight auxiliary registers (AR0 through AR7), each

of which can be loaded with a 16-bit value from data memory or directly from

an instruction word. Each auxiliary register value can also be stored in data

memory. The auxiliary registers are referenced by a 3-bit auxiliary register

pointer (ARP) embedded in status register ST0.

TMS320F Scheda tecnica(PDF) 32 Page - Texas Instruments