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HIP4080IP Scheda tecnica(PDF) 19 Page - Intersil Corporation

Il numero della parte HIP4080IP
Spiegazioni elettronici  80V/2.5A Peak, High Frequency Full Bridge FET Driver
PDF  21 Pages
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Produttore elettronici  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

HIP4080IP Scheda tecnica(HTML) 19 Page - Intersil Corporation

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Timing Diagrams
NOTE:
7. ALI and/or BLI may be high after t1, whereupon the ENABLE pin
may also be brought high.
FIGURE 38.
NOTE:
8. Between t1 and t2 the IN+ and IN- inputs must cause the OUT pin
to go through one complete cycle (transition order is not
important). If the ENABLE pin is low after the undervoltage
circuit is satisfied, the ENABLE pin will initiate the 10ms time
delay during which the IN+ and IN- pins must cycle at least once.
FIGURE 39.
VDD
DIS
ALI, BLI
8.5V TO 10.5V (ASSUMES 5% RESISTORS)
1.7V
12V, FINAL VALUE
VDD
DIS
LDEL
=10ms
t1
t2
8.3V TO 9.1V (ASSUMING 5% ZENER TOLERANCE)
12V, FINAL VALUE
5.1V
HIP4080



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