IMX7DCEC datasheet(65/161 Pages) NXP

Il numero della parte	IMX7DCEC

Spiegazioni elettronici	i.MX 7Dual Family of Applications Processors Datasheet

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Electrical characteristics

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

MAXDTI MAXIMUM delay from

EIM_DTACK_B to its internal

FF + 2 cycles for

synchronization

—

WE47

EIM_DTACK_B Active to

EIM_CSx_B Invalid

MAXCO – MAXCSO +

MAXDTI

MAXCO –

MAXCSO +

MAXDTI

—

WE48

EIM_CSx_B Invalid to

EIM_DTACK_B Invalid

—

1 For more information on configuration parameters mentioned in this table, see the i.MX 7Dual Application Processor Reference

Manual (IMX7DRM).

2 In this table, CSA means WCSA when write operation or RCSA when read operation.

3 In this table, CSN means WCSN when write operation or RCSN when read operation.

4 t is axi_clk cycle time.

5 In this table, ADVN means WADVN when write operation or RADVN when read operation.

6In this table, ADVA means WADVA when write operation or RADVA when read operation.

Table 46. EIM asynchronous timing parameters table relative chip to select(continued)

Ref No.

Parameter

Determination by

Synchronous measured

parameters1

Min

Max

Unit

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